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PI6CDBL401B PDF预览

PI6CDBL401B

更新时间: 2024-11-20 01:12:23
品牌 Logo 应用领域
百利通 - PERICOM PC
页数 文件大小 规格书
16页 1121K
描述
4-Output Low Power PCIE GEN1-2-3 Buffer

PI6CDBL401B 数据手册

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PI6CDBL401B  
4-Output Low Power PCIE GEN1-2-3 Buffer  
Features  
Description  
Î4x 100MHz low power HCSL or LVDS compatible outputs  
ÎPCIe 3.0, 2.0 and 1.0 compliant  
e PI6CDBL401B is a 4-output low power buffer for 100MHz  
PCIe Gen1, Gen2 and Gen3 applications with integrated output  
terminations providing Zo=100Ω. e device has 4 output en-  
ables for clock management, and 3 selectable SMBus addresses.  
ÎProgrammable output amplitude and slew rate  
ÎCore supply voltage of 3.3V +/-10%  
ÎOutput supply voltage of 1.8V, 2.5V and 3.3V  
ÎIndustrial ambient operation temperature  
ÎAvailable in lead-free package: 32-TQFN  
Applications  
ÎPCIe 3.0/2.0/1.0 clock distribution  
Block Diagram  
OE(3:0)#  
4
CLK(3:0)  
CLK_IN  
ZDB PLL  
CLK_IN#  
SADR_tri  
HIBW_BYPM_LOBW#  
CONTROL  
LOGIC  
CKPWRGD_PD#  
SDATA_3.3  
SCLK_3.3  
All trademarks are property of their respective owners.  
www.pericom.com  
PI6CDBL401B  
Rev.C  
03/23/16  
16-0064  
1

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