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PI6C9911E-5IJX PDF预览

PI6C9911E-5IJX

更新时间: 2024-11-19 20:52:07
品牌 Logo 应用领域
百利通 - PERICOM 驱动逻辑集成电路
页数 文件大小 规格书
9页 643K
描述
PLL Based Clock Driver, 6C Series, 8 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32

PI6C9911E-5IJX 技术参数

生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
系列:6C输入调节:STANDARD
JESD-30 代码:R-PQCC-J32长度:13.97 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:RECTANGULAR
封装形式:CHIP CARRIER认证状态:Not Qualified
Same Edge Skew-Max(tskwd):1.2 ns座面最大高度:3.55 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.43 mm最小 fmax:125 MHz
Base Number Matches:1

PI6C9911E-5IJX 数据手册

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PI6C9911 & PI6C9911E  
5V High-Speed Programmable Skew  
Clock Buffers - SuperClock  
Product Features  
Description  
Four pairs of programmable skew outputs  
User-selectable output functions:  
Selectable skews  
The PI6C9911 and PI6C9911E are low-skew, low jitter, 5V phase-  
lock-loop (PLL) programmable skew clock drivers, for  
high-performance computing and networking applications. These  
parts offer user-selectable skew-control of 4 output pairs, provid-  
ing the timing delays necessary to optimize high-performance  
clock-distribution circuits.  
Inverted and noninverted  
Operation at ½ and ¼ input frequency  
Operation at 2X and 4X input frequency  
Low skew <100ps typical same pair, 250ps max.  
Allow REF clock input to have Spread Spectrum  
modulation for EMI reduction  
Each output can be hardwired to one of nine delay or function  
configurations. Delay increments are determined by the input clock  
frequency and the configurations selected by the user.  
The PI6C9911 and PI6C9911E allow the REF clock input to have  
Spread Spectrum modulation for EMI reduction.  
2X, 4X, ½ and ¼ outputs  
3-level inputs for skew and output frequency control  
External feedback, internal loop filter  
Low cycle-to-cycle Jitter: <25ps RMS  
Duty cycle of output clock signals: 45% min. 55% max.  
Same pinout as Cypress CY7B9911  
Available in 32-pin PLCC Package (J)  
Both buffers are pin-compatable with Cypress’s RoboClock  
CY7B9911, but with improvedAC/DC characteristics.  
The PI6C9911 and PI6C9911E also have the same pinout as  
Cypress’s CY7B9911and with balanced output drive.  
Output Operation  
3.75 to 100 MHz for PI6C9911  
3.75 to 125 MHz for PI6C9911E  
Logic Block Diagram  
Pin Configuration  
4
3
2
1
32 31 30  
29  
3F1  
4F0  
5
6
7
8
9
2F0  
28  
27  
26  
25  
24  
23  
22  
21  
GND  
1F1  
4F1  
32-Pin  
J
VCCQ  
VCCN  
4Q1  
1F0  
VCCN  
1Q0  
1Q1  
GND  
GND  
10  
11  
12  
13  
4Q0  
GND  
GND  
14 15 16 17 18 19 20  
PS8451B  
03/28/01  
1

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