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PI6C991-JI PDF预览

PI6C991-JI

更新时间: 2024-09-30 23:27:39
品牌 Logo 应用领域
其他 - ETC 时钟驱动器逻辑集成电路信息通信管理
页数 文件大小 规格书
9页 529K
描述
Eight Distributed-Output Clock Driver

PI6C991-JI 数据手册

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PI6C991  
5V High-Speed Programmable  
Skew Clock Buffer - SuperClockTM  
Product Features  
Description  
Four pairs of programmable skew outputs  
3.75 to 80 MHz output operation  
The PI6C991 is a low-skew, low jitter, 5V phase-lock loop (PLL)  
programmable skew clock driver, for high performance comput-  
ing and networking applications. This part offers user selectable  
skew-control of 4 output pairs, providing the timing delays neces-  
sary to optimize high performance clock distribution circuits.  
User-selectable output functions:  
Selectable skews  
Inverted and noninverted  
Each output can be hardwired to one of nine delay or function  
configurations. Delay increments are determined by the input clock  
frequency and the configurations selected by the user.  
Operation at ½ and ¼ input frequency  
Operation at 2X and 4X input frequency  
Low skew <100ps typical, same pair. 250ps max.  
Allow REF clock input to have Spread Spectrum  
modulation for EMI reduction  
The PI6C991 allows the REF clock input to have Spread Spectrum  
modulation for EMI reduction.  
The PI6C991 is pin-compatible with Cypress RoboClock CY7B991,  
with improvedAC/DC characteristics.  
2X, 4X, ½ and ¼ outputs  
3-level inputs for skew and output frequency control  
External feedback, internal loop filter  
Low cycle-to-cycle Jitter: <25ps RMS  
Duty cycle of output clock signals: 45% min. 55% max.  
Compatible with Pentium based processor  
Same pinout as Cypress CY7B991  
Packaged in Plastic 32-pin PLCC Package  
Logic Block Diagram  
Pin Configuration  
32-Pin  
J
PS8448  
01/27/00  
1

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