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PI6C9930H PDF预览

PI6C9930H

更新时间: 2024-11-18 23:27:39
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其他 - ETC 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 353K
描述
Eight Distributed-Output Clock Driver

PI6C9930H 数据手册

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PI6C9930  
3.3V Zero-Delay Clock Buffer  
Features  
ProductDescription  
The PI6C9930 Clock Buffer offers zero-delay, low-skew system  
clockdistribution.Thesemultipleoutputclockdriversoptimizethe  
timing of high-performance computer systems. Each of eight  
individual drivers can drive series-terminated transmission lines  
with impedances as low as 50while delivering minimal output  
skews and full-swing logic levels.  
Near zero input to output delay  
Seven copies of the REF/2 or  
Six copies of REF plus one REF × 2  
25 – 100 MHz output  
50% duty cycle  
ConnectingQ0toFBprovidesREF/2outputsonQ1-Q7.Connecting  
any of Q1 - Q7 output to FB produces six copies of the REF input  
plus one REF x 2 on Q0.  
Lowskew  
Lowjitter(<250pscycle-to-cycle)  
Low noise balanced drive outputs  
V =3.3V±0.3V, T =0°to70°  
CC  
A
Test Mode  
24-pin209milwideSSOP(H)  
24-pin150milwideQSOP(Q)  
24-pin300milwideSOIC(S)  
In normal system operation, this pin is connected to ground. For  
testing purposes, the TEST pin can have a removable jumper to  
ground,orbetiedLOWthrougha100resistor.Thiswillallowdrive  
by an external tester. If the TEST input is forced HIGH, the device  
will operate with its internal phase-locked loop disconnected, and  
input levels supplied to REF will directly control all outputs.  
Relativeoutputtooutputfunctionsarethesameasinnormalmode.  
Applications  
PCI 66 MHz or 33 MHz systems  
Block Diagram  
Pinout  
24-Pin  
H, Q, S  
PS8096B 01/25/99  
177  

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