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PI6C39911A-5 PDF预览

PI6C39911A-5

更新时间: 2024-09-29 23:27:39
品牌 Logo 应用领域
其他 - ETC 时钟
页数 文件大小 规格书
11页 273K
描述
Clock IC | 500ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz

PI6C39911A-5 数据手册

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PI6C39911A  
3.3V High Speed LVTTL or Balanced Output  
Programmable Skew Clock Buffer - SuperClock®  
Features  
Description  
• All output pair skew <100ps typical (250 Max.)  
• 12.5 MHz to 133 MHz output operation  
The PI6C39911A offers selectable control over system clock func-  
tions. These multiple-output clock drivers provide the system  
integrator with functions necessary to optimize the timing  
• 3.125 MHz to 133 MHz input operation (input as low as 3.125  
of high-performance computer systems. Eight individual drivers,  
arranged as four pairs of user-controllable outputs, can each drive  
terminated transmission lines with impedances as low as 50-Ohms  
whiledeliveringminimalandspecifiedoutputskewsandfull-swing  
logiclevels.  
MHzfor4xoperation,or6.25MHzfor2xoperation)  
• User-selectable output functions  
— Selectable skew to 18ns  
— Inverted and non-inverted  
— Operation at ½ and ¼ input frequency  
— Operation at 2X and 4X input frequency  
• Zero input-to-output delay  
• 50% duty-cycle outputs  
• Inputs are 5V Tolerant  
• LVTTLoutputsdrive50Ohmterminatedlines  
• Operates from a single 3.3V supply  
• Low operating current  
• 32-pinPLCCpackage  
• Jitter < 200ps peak-to-peak (< 25ps RMS)  
• PI6C39911Aisapin-to-pincompatiblewithCY7B9911V  
Each output can be hardwired to one of nine skews or function  
configurations. Delay increments of 0.7ns to 1.5ns are determined  
by the operating frequency with outputs able to skew up to ±6 time  
units from their nominal “zero” skew position. The completely  
integrated PLL allows external load and transmission line delay  
effects to be canceled. The user can create output-to-output skew  
of up to ±12 time units.  
Divide-by-two and divide-by-four output functions are provided  
for additional flexibility in designing complex clock systems.  
WhencombinedwiththeinternalPLL,thesedividefunctionsallow  
distribution of a low-frequency clock that can be multiplied by two  
orfourattheclockdestination. This feature allows flexibility and  
simplifies system timing distribution design for complex high-  
speed systems.  
PinConfiguration  
LogicBlockDiagram  
Test  
Phase  
Freq.  
DET  
VCO and  
Time Unit  
Generator  
FB  
Filter  
REF  
FS  
4
3
2
1
32 31 30  
5
29  
28  
27  
26  
25  
24  
23  
22  
21  
3F1  
4F0  
4F1  
2F0  
GND  
1F1  
1F0  
6
7
4Q0  
4Q1  
4F0  
4F1  
32 Pin  
J
8
V
CCQ  
Select Inputs  
(three level)  
9
V
V
CCN  
4Q1  
CCN  
Skew  
10  
11  
12  
13  
1Q0  
1Q1  
GND  
GND  
3Q0  
3Q1  
3F0  
3F1  
4Q0  
Select  
GND  
GND  
2Q0  
2Q1  
2F0  
2F1  
14 15 16 17 18 19 20  
Matrix  
1Q0  
1Q1  
1F0  
1F1  
PS8627A  
02/07/03  
1

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