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PI3PCIE2612-AZFE PDF预览

PI3PCIE2612-AZFE

更新时间: 2024-11-05 06:03:11
品牌 Logo 应用领域
百利通 - PERICOM 解复用器逻辑集成电路PC
页数 文件大小 规格书
18页 708K
描述
High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout

PI3PCIE2612-AZFE 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Transferred零件包装代码:QFN
包装说明:VQCCN,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:4.27
Is Samacsys:N系列:3PCIE
JESD-30 代码:R-XQCC-N56JESD-609代码:e3
长度:11 mm逻辑集成电路类型:MULTIPLEXER
功能数量:4输入次数:4
输出次数:1端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:UNSPECIFIED
封装代码:VQCCN封装形状:RECTANGULAR
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:0.8 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:5 mmBase Number Matches:1

PI3PCIE2612-AZFE 数据手册

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PI3PCIE2612-A  
High Bandwidth, 6-Differential Channel  
1:2 DP/PCIe Gen2 Display Mux, ATX Pinout  
Features  
Description  
• 6 Differential Channel, 1 to 2 demux that will support  
5.0Gbps PCIexpress Gen2 signals on one path, and DP 1.1  
signals on the second path  
Pericom Semiconductor’s PI3PCIE2612-A one to two Mux/  
Demux is targeted for next generation systems that combine PCI-  
Express gen-II signals with Display Port Signals.  
• Insertion Loss for high speed channels @ 5.0 Gbps: -5.0dB  
• Low Bit-to-Bit Skew , 7ps max (between '+' and '-' bits)  
• Latched Mux Select  
Application  
Routing DPand PCIExpress Gen1 or Gen2 signals with low signal  
attenuation.  
• Matched paths for all PCIe signals  
• Low Crosstalk for high speed channels: -35dB@2.5 GHz  
• Low Off Isolation for high speed channels: -35dB@2.5 GHz  
• V Operating Range: 3.3V ± 10%  
DD  
• ESD Tolerance: 8kV contact on Display Port Path output  
4kV HBM on PCI-Express path output  
• Low channel-to-channel skew, 35ps max  
• Packaging (Pb-free & Green):  
Pin Diagram (top-side view)  
– 56 TQFN (ZFE)  
Block Diagram  
GND  
Tx2+  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
IN_0+  
IN_0+  
D0+  
D0  
D1+  
D1  
-
IN_0  
IN_1+  
-
3
IN_0-  
Tx2-  
4
Tx3+  
IN_1+  
IN_1-  
-
IN_1  
-
5
Tx3-  
IN_2+  
IN_2-  
IN_3+  
IN_3-  
D2+  
D2-  
D3+  
D3-  
6
VDD  
D0+  
D0-  
7
IN_2+  
8
IN_2-  
Tx0+  
Tx0-  
Tx1+  
Tx1 -  
D1+  
D1-  
9
IN_3+  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
D2+  
IN_3-  
GND  
Tx2+  
Tx2-  
Tx3+  
Tx3-  
D2-  
D3+  
D3-  
OUT+  
OUT-  
X+  
OUT+  
AUX+  
AUX-  
HPD  
NC  
GND  
VDD  
OUT  
-
X+  
X-  
X-  
GND  
VDD  
Rx0+  
Rx0-  
Rx0+  
Rx0-  
Rx1+  
Rx1-  
SEL  
LE#  
Rx1+  
Rx1-  
GND  
GND  
SEL  
LE#  
Logic  
Control  
Truth Table (SEL control)  
Function  
Truth Table (Latch control)  
SEL  
LE#  
Internal mux select  
PCI-Express Gen2 path is active (Tx)  
Digital Video Port is active (Dx)  
L
0
1
Respond to changes on SEL  
Latched  
H
PS8925B  
11/30/07  
1
07-0261  

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