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PI3PCIE3412ZHEX PDF预览

PI3PCIE3412ZHEX

更新时间: 2024-11-06 20:07:55
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
10页 1466K
描述
Differential Multiplexer, 2 Func, GREEN, MO-220, TQFN-42

PI3PCIE3412ZHEX 技术参数

生命周期:Transferred包装说明:HVQCCN,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.66
模拟集成电路 - 其他类型:DIFFERENTIAL MULTIPLEXERJESD-30 代码:R-XQCC-N42
长度:9 mm信道数量:2
功能数量:2端子数量:42
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
座面最大高度:0.84 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES最长断开时间:25 ns
最长接通时间:25 ns温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:3.5 mm
Base Number Matches:1

PI3PCIE3412ZHEX 数据手册

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PI3PCIE3412  
3.3V, PCI Express® 3.0 2-Lane,  
2:1 Mux/DeMux Switch, with Single Enable  
Description  
Features  
•ꢀ 4ꢀDifferentialꢀChannel,ꢀ2:1ꢀMux/DeMuxꢀ  
•ꢀ PCIꢀExpress®ꢀ3.0ꢀPerformance,ꢀ8.0Gbps  
•ꢀ Bi-directionalꢀOperation  
•ꢀ LowꢀBit-to-BitꢀSkew,ꢀ10psꢀmax  
•ꢀ Lowꢀchannel-to-channelꢀskew,ꢀ20psꢀmax  
•ꢀ LowꢀCrosstalk:ꢀ-35dB@4ꢀGHz  
•ꢀ HighꢀOffꢀIsolation:ꢀꢀ-22dB@4ꢀGHzꢀ(8.0Gbps)  
•ꢀ Lowꢀinsertionꢀloss:ꢀ-1.3dB@4ꢀGHzꢀ(8.0Gbps)  
•ꢀ Returnꢀloss:ꢀ-21dB@4ꢀGHz  
PericomꢀSemiconductor’sꢀPI3PCIE3412ꢀisꢀanꢀ8ꢀtoꢀ4ꢀdifferentialꢀ  
channelꢀ multiplexer/demultiplexerꢀ switch.ꢀ Thisꢀ solutionꢀ canꢀ  
switch2fullPCIExpress®3.0,lanestooneoftwolocations.ꢀ  
Usingꢀ aꢀ uniqueꢀ designꢀ technique,ꢀ Pericomꢀ hasꢀ beenꢀ ableꢀ toꢀ  
minimizetheimpedanceoftheswitchsuchthattheattenuationꢀ  
observedꢀ throughꢀ theꢀ switchꢀ isꢀ mininal.ꢀ ꢀ Theꢀ uniqueꢀ designꢀ  
techniquealsooffersalayouttargetedforPCIExpresssignals,ꢀ  
whichꢀminimizesꢀtheꢀchannelꢀtoꢀchannelꢀskewꢀasꢀwellꢀasꢀchannelꢀ  
toꢀchannelꢀcrosstalkꢀasꢀrequiredꢀbyꢀtheꢀPCIꢀExpressꢀspecification.  
PI3PCIE3412ꢀcanꢀalsoꢀbeꢀusedꢀforꢀapplicationꢀupꢀtoꢀ12Gbps  
•ꢀ SupportꢀforꢀDP1.2ꢀ-ꢀHBR2,ꢀHBR,ꢀRBR  
•ꢀ SupplyꢀVoltageꢀ3.3Vꢀ  
•ꢀ Packagingꢀ(Pb-freeꢀ&ꢀGreen):ꢀꢀ  
ꢀꢀ –ꢀ42-contact,ꢀTQFNꢀ(ZH42)ꢀ  
Application  
RoutingꢀofꢀPCIꢀExpressꢀ3.0,ꢀDP1.2,ꢀUSB3.0,ꢀSAS2.0,ꢀSATA3.0,ꢀ  
XAUI,ꢀRXAUIꢀsignalsꢀwithꢀlowꢀsignalꢀattenuation.  
Pin Configuration (Top-side view)  
Block Diagram  
A0+  
A0-  
A1+  
A1-  
B0+  
B0-  
B1+  
B1-  
C0+  
C0-  
C1+  
C1-  
42 41 40 39  
GND  
A0+  
A0-  
B0+  
B0-  
B1+  
B1-  
C0+  
C0-  
C1+  
C1-  
VDD  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
1
2
3
GND  
VDD  
4
5
A1+  
A1-  
6
B2+  
B2-  
B3+  
B3-  
C2+  
C2-  
C3+  
C3-  
A2+  
A2-  
A3+  
A3-  
7
VDD  
8
SEL  
GND  
A2+  
A2-  
9
B2+  
B2-  
B3+  
B3-  
C2+  
C2-  
C3+  
C3-  
10  
11  
12  
13  
14  
15  
16  
17  
VDD  
GND  
A3+  
A3-  
SEL  
GND  
Truth Table  
18 19 20 21  
Function  
SEL  
L
A ꢀtoꢀB  
N
N
A to C  
H
Nꢀ  
N
1
www.pericom.com  
04/15/13  
13-0046  

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