Datasheet > PHP11N06LT

PHP11N06LT

更新时间： 2024-11-05 22:26:31

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管
页数	文件大小	规格书
12页	116K
描述
N-channel TrenchMOS transistor Logic level FET

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PHP11N06LT 数据手册

Philips Semiconductors

Product specification

N-channel TrenchMOS transistor

Logic level FET

PHP11N06LT, PHB11N06LT

PHD11N06LT

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

• Low on-state resistance

• Fast switching

V_DSS= 55 V

I_D= 10.5 A

• Logic level compatible

R_DS(ON)≤ 150 mΩ (V_GS= 5 V)

R_DS(ON)≤ 130 mΩ (V_GS= 10 V)

GENERAL DESCRIPTION

N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies

The PHP11N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB11N06LT is supplied in the SOT404 (D²PAK) surface mounting package.

The PHD11N06LT is supplied in the SOT428 (DPAK) surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404 (D²PAK)

SOT428 (DPAK)

tab

DESCRIPTION

tab

gate

drain ¹

source

1 2 3

tab drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

V_GSM

I_D

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Pulsed gate-source voltage T_j≤ 150˚C

T_j= 25 ˚C to 175˚C

T_j= 25 ˚C to 175˚C; R_GS= 20 kΩ

± 15

± 20

10.3

7.3

Continuous drain current

T_mb= 25 ˚C

_mb= 100 ˚C

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total power dissipation

Operating junction and

storage temperature

T_mb= 25 ˚C

175

˚C

- 55

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

August 1999

Rev 1.000

12 3 4 5 6 7...12

中文翻译

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