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PEX8548S-AA25BIG PDF预览

PEX8548S-AA25BIG

更新时间： 2024-01-03 00:18:36
品牌 Logo 应用领域
PLX /
页数 文件大小 规格书
4页 314K
描述
Micro Peripheral IC,

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PEX8548S-AA25BIG 技术参数

生命周期：Transferred包装说明：,
Reach Compliance Code：unknown风险等级：5.63
Base Number Matches：1

PEX8548S-AA25BIG 数据手册

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Low Power with Granular SerDes Control  
The PEX 8548 provides low power capability that is  
fully compliant with the PCI Express power  
management specification. In addition, the SerDes  
physical links can be turned off when unused for even  
lower power.  
advanced error reporting features make it suitable for  
High Availability (HA) applications. Three  
downstream ports include a Standard Hot Plug  
Controller. If the PEX 8548 is used in an application  
where one or more of its downstream ports connect to  
PCI Express slots, each port’s Hot Plug Controller can  
be used to manage the hot-plug event of its associated  
slot. Furthermore, its upstream port is a hot-plug client,  
allowing it to be used on hot-pluggable adapter cards,  
backplanes, and fabric modules.  
Flexible Port Width Configuration  
The width of each port can be individually configured  
through auto-negotiation, hardware strapping, host  
software configuration, I2C interface, or through an  
optional EEPROM.  
Fully Compliant Power Management  
For applications that require power management, the  
PEX 8548 device supports both link (L0, L0s, L1, L2/L3  
Ready, and L3) and device (D0 and D3hot) power  
management states, in compliance with the PCI Express  
power management specification.  
The PEX 8548 supports a large number of port  
configurations (see Figure 1). For example, if you are  
using the PEX 8548 in a fan-out application, you may  
configure the upstream port as a x16 and the  
downstream as eight x4 ports; three x8 ports & two x4  
ports; or various combinations, as long as you don’t run  
out of lanes (48) or ports (9). For a dual-graphics  
application, the device can be configured as three x16  
ports.  
SerDes Power and Signal Management  
The PEX 8548 supports software control of the SerDes  
outputs to allow optimization of power and signal  
strength in a system. The PLX SerDes implementation  
supports four levels of power – off, low, typical, and  
high. The SerDes block also supports loop-back modes  
and advanced reporting of error conditions, which  
enables efficient debug and management of the entire  
system.  
x16  
x16  
PEX 8548  
PEX 8548  
Applications  
x8x8x4x4x4x4  
x8  
x8 x8 x8 x4 x4  
x16  
Suitable for host-centric as well as peer-to-peer traffic  
patterns, the PEX 8548 can be configured for a wide  
variety of form factors and applications.  
Host Centric Fan-out  
The PEX 8548, with its symmetric or asymmetric lane  
configuration capability, allows user-specific tuning to a  
variety of host-centric applications.  
PEX 8548  
PEX 8548  
all x8  
x16 x16  
CPU  
Figure 1. Common Port Configurations  
Low Packet Latency  
Memory  
The PEX 8548 supports packet cut-thru with a  
maximum packet latency of 110ns between symmetric  
x16 ingress and egress ports. The low latency enables  
applications to achieve high throughput and  
performance. In addition to low latency, the device  
supports a packet payload size of up to 1024 bytes,  
enabling the user to achieve even higher throughput.  
Chip Set  
x8 or x16  
PEX 8548  
x8  
x8  
x4  
End  
Point  
Hot Plug for High Availability  
Hot plug capability allows users to replace hardware  
modules and perform maintenance without powering  
down the system. The PEX 8548 hot plug capability and  
Figure 2. Fan-in/out Usage  
1234

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