Version 1.2 2007
.
Features
PEX 8509 General Features
o 8-lane PCI Express switch
- PCIe Gen 1 (2.5Gbps) Integrated
SerDes
PEX 8509
o Up to eight ports (x1, x2, x4)
o 15mm x 15mm, 196-ball PBGA pkg.
o Typical Power: 1.2 Watts
®
Flexible & Versatile PCI Express Switch
Low-Power 8-Lane, 8-Port ExpressLaneTM PCIe Switch
The PEX 8509 device offers PCI Express switching capability conforming to the PCI
Express Base specification revision 1.1. This device enables users to add scalable
high bandwidth, non-blocking interconnects at the lowest cost to a wide variety of
applications including communications platforms, consumer products, servers,
storage systems, blade servers, industrial systems and embedded-control products.
The PEX 8509 can be used as a fan-out, aggregation, or peer-to-peer switch, and is
well-suited for Control Plane Applications, Docking Stations, DVRs, Multi-
Function Printers, Industrial Control Systems, Medical Imaging Systems,
Embedded Systems and AMC modules.
PEX 8509 Key Features
o Standards Compliant
- PCI Express Base Specification, r1.1
- PCI Power Management Interface
Specification r1.2
o High Performance
- Cut-through with low packet latency
- Max Payload Size of 1024 Bytes
- Non-blocking switch fabric
- Full line rate on all ports
o Flexible Configuration
- 8 flexible and configurable ports (x1,
x2 or x4)
- Lane and polarity reversal
- Configurable through I2C, Host
software, EEPROM or strapping pins
o PCI Express Power Management
- Link power management states: L0,
L0s, L1, L2/L3 Ready, and L3
- Device states: D0 and D3hot
o Quality of Service (QoS)
- One Virtual Channel per port
- Eight Traffic Classes per port
- Weighted Round-Robin Ingress Port
Arbitration
o Reliability, Availability,
Serviceability
- 3 standard Hot-Plug controllers
supporting PCI SHPC spec r1.0
- Transaction layer end-to-end CRC
- Poison bit support
- Basic and Advanced Error Reporting
support
- Per port error diagnostics
Port Configurations
The PEX 8509 offers eight lanes and up to eight ports supporting x1, x2 and x4 lane
widths. The ports can be configured for symmetric (each port having the same lane
width and traffic load) or asymmetric (ports having different lane widths). In the
event of asymmetric traffic, the PEX 8509 features a flexible central packet
memory that allocates a memory buffer for each port as required by the application
or endpoint. This buffer allocation along with the device's flexible packet flow
control minimizes bottlenecks when the upstream and aggregated downstream
bandwidths do not match (are asymmetric).
High Performance
The PEX 8509 architecture supports packet cut-thru with low latency (118ns).
This, combined with large packet memory (up to 1024 byte maximum payload
size) and non-blocking internal switch architecture, provides full line rate on all
ports for performance hungry applications such as docking stations, control planes,
embedded systems and AMC modules.
End-to-End Packet Integrity
The PEX 8509 provides end-to-end CRC protection (ECRC) and Poison-bit
support to enable designs that require end-to-end data integrity. These features are
optional in the PCI Express specification, but PLX provides them across its entire
ExpressLane switch product line.
Configuration Flexibility
The PEX 8509 provides several ways to configure its operations. The device can be
configured through strapping pins, I2C interface, CPU configuration cycles, or an
optional serial EEPROM. This allows for easy debug during the development phase,
performance monitoring during the operation phase, and driver or software upgrade.
• Bad DLLPs
• Bad TLPs
• CRC errors and more
- Fatal Error (FATAL_ERR#) signal
(legacy SERR equivalent)
- INTA# signal
Interoperability
The PEX 8509 is designed to be fully compliant with the PCI-SIG PCI Express base
specification revision 1.1. Additionally, it supports auto-negotiation, lane reversal,
and polarity reversal. The PEX 8509 also undergoes extensive Interoperability
testing in PLX’s Interoperability Lab.
- Port status bits
- Eight software controllable General
Purpose Output (GPO) signals
- JTAG boundary scan
Low Power with Granular SerDes Control
The PEX 8509 provides low power capability that is fully compliant with the PCI
Express power management specification. For even lower power, the SerDes
physical links can be programmed for desired power or turned off when unused.
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