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PEX8111RDK-F PDF预览

PEX8111RDK-F

更新时间： 2024-11-23 06:00:15
品牌 Logo 应用领域
PLX PC
页数 文件大小 规格书
2页 116K
描述
PCI Express to PCI Bridge

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中文翻译

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PEX8111RDK-F 数据手册

 浏览型号PEX8111RDK-F的Datasheet PDF文件第2页 
Version 1.4 2005  
PEX 8111  
Features  
ƒ General Features  
o Forward and Reverse bridging  
o144-ball BGA package with standard  
1.0 mm pitch (13mm x 13mm)  
oAlternative fine-pitch BGA package  
(10mm x 10mm)  
ExpressLane™ PCI Express to PCI Bridge  
Reversible Bridge in a Tiny Package  
o Low power – 400 milliwatts  
oEEPROM configuration option with  
SPI  
o Internal 8Kbyte shared RAM  
o 1.5 V core supply voltage  
o JTAG  
The PLX Technology PEX 8111 bridge enables designers to migrate legacy PCI bus  
interfaces to the new advanced serial PCI Express. This is ideal for including  
existing PCI ICs on a PCI Express™ Adapter Board, such as the new ExpressCard™  
or AdvancedMC™ standards. Both the standard BGA package and the tiny 10mm x  
10mm fine-pitch package offering make the PEX 8111 bridge well suited for  
applications where board real estate is at a premium. With its low power 0.15 micron  
CMOS design, the PEX 8111 consumes only about 400 mW of power.  
o Four (4) GPIO pins for maximum  
design flexibility  
o Extensive PME support including  
D0 and D0Active, D1, D2 and D3Hot  
and D3Cold  
Forward and Reverse Bridging  
The PEX 8111 supports forward and reverse bridging as defined by the  
PCI Express-to-PCI/PCI-X Bridge Specification 1.0. In forward mode, the bridge  
allows legacy PCI chips and adapters to be used with new PCI Express processor  
systems. Reverse bridge operation allows conventional PCI processors and chipsets  
to configure and control advanced PCI Express switches and endpoints. The reverse  
PEX 8111 not only allows complete configuration of a downstream PCI Express  
system from the PCI bus, but it also handles limited PCI Express root functions for  
reverse interrupt and Power Management Events.  
o Lead-free packaging available  
ƒ Integrated PCI Express Interface  
o PCI Express Base 1.0a compliant  
o x1 Link, dual-simplex, 2.5 Gbps per  
direction  
o One virtual channel  
o Automatic LVDS polarity reversal  
o 128 byte maximum payload size  
o Link CRC  
o Link power management  
o Flow control buffering  
PCI Bus (32-bit, 33/66 MHz)  
Block Diagram  
The PEX 8111 is equipped with a  
standard PCI Express port that  
operates as a single, x1 link with a  
maximum of 250 Megabytes per  
o PCI Express transaction queues for  
eight (8) outstanding TLPs  
ƒ PCI Interface  
second of throughput per transmit  
PCI Master and Target Interface Logic  
o PCI v.3.0: 32 bits, up to 66 MHz  
o PCI Power Management 1.1  
o Internal arbiter supports up to 4  
external masters; REQ#/GNT#  
signals  
and receive direction. The single 2.5  
Gbps integrated SerDes delivers the  
highest bandwidth with the lowest  
possible pin count using LVDS  
technology.  
Configuration  
Registers  
8K Shared  
RAM  
FIFOs  
o 3.3V I/O and 5V tolerant PCI  
o Message Signal Interrupt (MSI)  
support  
o Provides PCI clock output  
o Four mailbox registers for messaging  
o VGA and ISA Enable registers for  
legacy operation  
PCI Express Transaction Layer  
(Packet Construction Logic)  
The PEX 8111 has a single parallel  
bus segment supporting the PCI v.3.0  
protocol, and a 32-bit wide parallel  
data path running up to 66MHz.  
PCI Express Data Link Layer  
PCI Express PHY Layer  
The device supports internal queues  
with flow control features to optimize  
throughput and traffic flow.  
j
PCI Express Link (1 lane, 2.5 GHz)  
Figure 1. PEX 8111 Block Diagram  
12

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