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PEX8505-AA25BIG PDF预览

PEX8505-AA25BIG

更新时间： 2024-11-26 06:00:15
品牌 Logo 应用领域
PLX 开关总线控制器微控制器和处理器外围集成电路PC
页数 文件大小 规格书
4页 480K
描述
Flexible & Versatile PCI Express® Switch

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PEX8505-AA25BIG 技术参数

生命周期：Transferred零件包装代码：BGA
包装说明：BGA,针数：196
Reach Compliance Code：unknown风险等级：5.71
Is Samacsys：N其他特性：ITS ALSO REQUIRES 3.3 V SUPPLY
总线兼容性：I2CJESD-30 代码：S-PBGA-B196
端子数量：196封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY表面贴装：YES
技术：CMOS端子形式：BALL
端子位置：BOTTOMuPs/uCs/外围集成电路类型：BUS CONTROLLER, PCI
Base Number Matches：1

PEX8505-AA25BIG 数据手册

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Version 1.0 2007  
.
Features  
PEX 8505  
ƒ PEX 8505 General Features  
o 5-lane PCI Express switch  
- Gen 1 (2.5Gbps) Integrated  
SerDes  
®
Flexible & Versatile PCI Express Switch  
o Up to 5 ports (x1, x2)  
o 15mm x 15mm, 196-ball PBGA pkg.  
o Typical Power: 0.8 Watts  
Low-Power 5-Lane, 5-Port ExpressLaneTM PCIe Switch  
The PEX 8505 device offers PCI Express switching capability conforming to the PCI  
Express Base specification revision 1.1. This device enables users to add scalable  
high bandwidth, non-blocking interconnects at the lowest cost to a wide variety of  
applications including communications platforms, consumer products, servers,  
storage systems, blade servers, industrial systems and embedded-control products.  
The PEX 8505 can be used as a fan-out, or peer-to-peer switch, and is well-suited  
for Control Plane Applications, I/O Expansion, Video Surveillance, Multi-  
Function Printers, DVRs, Industrial Control Systems, Medical Imaging  
Systems, Embedded Systems and AMC modules.  
ƒ PEX 8505 Key Features  
o Standards Compliant  
- PCI Express Base Specification, r1.1  
- PCI Power Management Interface  
Specification r1.2  
o High Performance  
- Cut-thru with low packet latency  
- Max Payload Size of 1024 Bytes  
- Non-blocking internal architecture  
- Full line rate on all ports  
o Flexible Configuration  
- Five flexible & configurable ports  
(x1, x2)  
- Lane and polarity reversal  
- Configurable with strapping pins,  
EEPROM, I2C or Host software  
o PCI Express Power Management  
- Link power management states: L0,  
L0s, L1, L2/L3 Ready and L3  
- Device states: D0 and D3hot  
o Quality of Service (QoS)  
- One Virtual Channel per port  
- Eight Traffic Classes per port  
- Weighted Round-Robin Ingress Port  
Arbitration  
o Reliability, Availability,  
Serviceability  
- 3 Standard Hot-Plug Controllers  
supporting PCI SHPC spec r1.0  
- Transaction layer end-to-end CRC  
- Poison bit support  
- Basic and Advanced Error Reporting  
support  
- Per port error diagnostics  
Port Configurations  
The PEX 8505 offers five lanes and up to five ports supporting x1 and x2 lane  
widths. The PEX 8505 features a flexible central packet memory that allocates a  
memory buffer for each port as required by the application or endpoint. This buffer  
allocation along with the device's flexible packet flow control minimizes  
bottlenecks when the upstream and aggregated downstream bandwidths do not  
match.  
High Performance  
The PEX 8505 architecture supports packet cut-thru with low latency (138ns).  
This, combined with large packet memory (up to 1024 byte maximum payload  
size) and non-blocking internal switch architecture, provides full line rate on all  
ports for performance hungry applications such as docking stations, control planes,  
embedded systems and AMC modules.  
End-to-End Packet Integrity  
The PEX 8505 provides end-to-end CRC protection (ECRC) and Poison-bit  
support to enable designs that require end-to-end data integrity. These features are  
optional in the PCI Express specification, but PLX provides them across its entire  
ExpressLane switch product line.  
Configuration Flexibility  
The PEX 8505 provides several ways to configure its operations. The device can be  
configured through strapping pins, I2C interface, CPU configuration cycles, or an  
optional serial EEPROM. This allows for easy debug during the development phase,  
performance monitoring during the operation phase, and driver or software upgrade.  
• Bad DLLPs  
• Bad TLPs  
• CRC errors and more  
Interoperability  
- Fatal Error (FATAL_ERR#) signal  
(legacy SERR equivalent)  
- INTA# signal  
The PEX 8505 is designed to be fully compliant with the PCI-SIG PCI Express base  
specification revision 1.1. Additionally, it supports auto-negotiation, lane reversal,  
and polarity reversal. The PEX 8505 also undergoes thorough Interoperability  
testing in PLX’s Interoperability Lab.  
- Port status bits  
- Eight software controllable General  
Purpose Output (GPO) signals  
- JTAG boundary scan  
Low Power with Granular SerDes Control  
The PEX 8505 provides low power capability that is fully compliant with the PCI  
Express power management specification. For even lower power, the SerDes  
physical links can be programmed for desired power or turned off when unused.  
www.plxtech.com  
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