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PEX8112-AA66BIF PDF预览

PEX8112-AA66BIF

更新时间： 2024-11-23 06:00:15
品牌 Logo 应用领域
PLX 总线控制器微控制器和处理器外围集成电路数据传输PC
页数 文件大小 规格书
2页 112K
描述
ExpressLane™ PCI Express to PCI Bridge

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中文翻译

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PEX8112-AA66BIF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：BGA
包装说明：BGA, BGA144,12X12,40针数：144
Reach Compliance Code：compliant风险等级：5.69
Is Samacsys：N地址总线宽度：
最大数据传输速率：250 MBps外部数据总线宽度：
JESD-30 代码：R-PBGA-B144端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA144,12X12,40封装形状：RECTANGULAR
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.5,3.3,3.3/5 V认证状态：Not Qualified
子类别：Bus Controllers最大压摆率：207 mA
标称供电电压：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
uPs/uCs/外围集成电路类型：BUS CONTROLLER, PCIBase Number Matches：1

PEX8112-AA66BIF 数据手册

 浏览型号PEX8112-AA66BIF的Datasheet PDF文件第2页 
Version 1.0 2007  
PEX 8112  
Features  
ƒ General Features  
o Forward and Reverse bridging  
o144-ball BGA package with standard  
1.0 mm pitch (13mm x 13mm)  
o161-ball BGA package with fine  
0.65 mm pitch (10mm x 10mm)  
oLow power – 400 milliwatts  
oEEPROM configuration option with  
SPI  
ExpressLane™ PCI Express to PCI Bridge  
Reversible Bridge in a Tiny Package  
The PLX Technology PEX 8112 bridge enables designers to migrate legacy PCI bus  
interfaces to the new advanced serial PCI Express. This is ideal for including  
existing PCI ICs on a PCI Express™ Adapter Board, such as the new ExpressCard™  
or AdvancedMC™ standards. The 13mm x 13mm standard BGA package or 10mm  
x 10mm fine BGA package offerings makes the PEX 8112 bridge well suited for  
applications where board real estate is at a premium. With its low power 0.15 micron  
CMOS design, the PEX 8112 consumes only about 400 mW of power.  
o Internal 8Kbyte shared RAM  
o 1.5 V core supply voltage  
o JTAG  
o Four (4) GPIO pins for maximum  
design flexibility  
o Extensive PME support including  
D0 and D0Active, D1, D2 and D3Hot  
and D3Cold  
o Lead-free packaging only  
o Industrial Temperature: -40 to +85ºC  
Forward and Reverse Bridging  
The PEX 8112 supports forward and reverse bridging as defined by the  
PCI Express-to-PCI/PCI-X Bridge Specification 1.0. In forward mode, the bridge  
allows legacy PCI chips and adapters to be used with new PCI Express processor  
systems. Reverse bridge operation allows conventional PCI processors and chipsets  
to configure and control advanced PCI Express switches and endpoints. The reverse  
PEX 8112 not only allows complete configuration of a downstream PCI Express  
system from the PCI bus, but it also handles limited PCI Express root functions for  
reverse interrupt and Power Management Events.  
ƒ Integrated PCI Express Interface  
o PCI Express Base 1.0a compliant  
o x1 Link, dual-simplex, 2.5 Gbps per  
direction  
o One virtual channel  
o Automatic LVDS polarity reversal  
o 128 byte maximum payload size  
o Link CRC  
o Link power management  
o Flow control buffering  
PCI Bus (32-bit, 33/66 MHz)  
Block Diagram  
The PEX 8112 is equipped with a  
standard PCI Express port that  
operates as a single, x1 link with a  
maximum of 250 Megabytes per  
o PCI Express transaction queues for  
eight (8) outstanding TLPs  
second of throughput per transmit  
PCI Master and Target Interface Logic  
ƒ PCI Interface  
and receive direction. The single 2.5  
Gbps integrated SerDes delivers the  
highest bandwidth with the lowest  
possible pin count using LVDS  
technology.  
o PCI v.3.0: 32 bits, up to 66 MHz  
o PCI Power Management 1.1  
o Internal arbiter supports up to 4  
external masters; REQ#/GNT#  
signals  
Configuration  
Registers  
8K Shared  
RAM  
FIFOs  
PCI Express Transaction Layer  
(Packet Construction Logic)  
o 3.3V I/O and 5V tolerant PCI  
o Message Signal Interrupt (MSI)  
support  
o Provides PCI clock output  
o Four mailbox registers for messaging  
o VGA and ISA Enable registers for  
legacy operation  
The PEX 8112 has a single parallel  
bus segment supporting the PCI v.3.0  
protocol, and a 32-bit wide parallel  
data path running up to 66MHz.  
PCI Express Data Link Layer  
PCI Express PHY Layer  
The device supports internal queues  
with flow control features to optimize  
throughput and traffic flow.  
j
PCI Express Link (1 lane, 2.5 GHz)  
Figure 1. PEX 8112 Block Diagram  
12

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