PDM41024
1 Megabit Static RAM
128K x 8-Bit
1
2
Description
Features
The PDM41024 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE1) inputs are both LOW and CE2 is
HIGH. Reading is accomplished when WE and CE2
remain HIGH and CE1 and OE are both LOW.
■ High-speed access times
Com’l: 10, 12 and 15 ns
Ind’l: 12 and 15 ns
■ Low power operation (typical)
- PDM41024SA
3
Active: 450 mW
Standby: 50 mW
- PDM41024LA
Active: 400 mW
The PDM41024 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41024 comes in two versions:
the standard power version (SA) and the low power
version (LA). The two versions are functionally the
same and differ only in their power consumption.
4
Standby: 25mW
■ Single +5V (±10%) power supply
■ TTL-compatible inputs and outputs
■ Packages
The PDM41024 is available in a 32-pin plastic TSOP
(I), and a 300-mil and 400-mil plastic SOJ.
5
Plastic SOJ (300 mil) - TSO
Plastic SOJ (400 mil) - SO
Plastic TSOP (I)- T
6
Functional Block Diagram
7
A0
Decoder
Memory
•
•
•
8
•
•
•
Addresses
Matrix
•
•
•
•
•
A16
9
• • • • •
Column I/O
I/O0
Input
Data
Control
•
•
10
11
12
I/O7
•
•
•
CE1
CE2
WE
OE
Control
Rev. 3.3 - 4/09/98
1