PRELIMINARY
PDM34089
3.3V 64K x 32 Fast CMOS
Synchronous Static RAM
with Burst Counter
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Description
Features
The PDM34089 is a 2,097,152 bit synchronous ran-
dom access memory organized as 65,536 x 32 bits. It
is designed with burst mode capability and interface
controls to provide high-performance in second
level cache designs for x86, Pentium, 680x0, and
PowerPC microprocessors. Addresses, write data
and all control signals except output enable are con-
trolled through positive edge-triggered registers.
Write cycles are self-timed and are also initiated by
the rising edge of the clock. Controls are provided to
allow burst reads and writes of up to four words in
length. A 2-bit burst address counter controls the
two least-significant bits of the address during burst
reads and writes. The burst address counter selec-
tively uses the 2-bit counting scheme required by the
x86 and Pentium or 680x0 and PowerPC micropro-
cessors as controlled by the mode pin. Individual
write strobes provide byte write for the four 8-bit
bytes of data. An asynchronous output enable sim-
plifies interface to high-speed buses.
■ Interfaces directly with the x86, Pentium™, 680X0
and PowerPC™ processors
■ Single 3.3V power supply
■ Mode selectable for interleaved or linear burst:
Interleaved for x86 and Pentium
Linear for 680x0 and PowerPC
■ Fast access times:
9, 10, 12 and 15 ns
■ High-density 64K x 32 architecture with burst
address counter
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■ Fully registered inputs
■ High-output drive: 30 pF at rated T
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■ Asynchronous output enable
■ Self-timed write cycle
■ Separate byte write enables and one global write
enable
■ Internal burst read/write address counter
■ Internal registers for address, data, controls
■ Burst mode selectable
■ Sleep mode
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■ Packages:
100-pin QFP - (Q)
100-pin TQFP - (TQ)
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TM
i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation.
Rev 1.1 - 5/01/98
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