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PDM31532LA12T PDF预览

PDM31532LA12T

更新时间: 2024-11-24 13:36:43
品牌 Logo 应用领域
IXYS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 283K
描述
Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, PLASTIC, TSOP2-44

PDM31532LA12T 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP44,.46,32针数:44
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.5
最长访问时间:12 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44长度:18.41 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.002 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.13 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

PDM31532LA12T 数据手册

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PDM31532  
64K x 16 CMOS  
3.3V Static RAM  
1
2
Features  
Description  
High-speed access times  
- Com’l: 9, 10, 12, 15 and 20 ns  
- Ind: 12, 15 and 20 ns  
Low power operation (typical)  
- PDM31532LA  
The PDM31532 is a high-performance CMOS static  
RAM organized as 65,536 x 16 bits. The PDM31532  
features low power dissipation using chip enable  
(CE) and has an output enable input (OE) for fast  
memory access. Byte access is supported by upper  
and lower byte controls.  
3
Active: 200 mW  
Standby: 10 mW  
- PDM31532SA  
Active: 250 mW  
The PDM31532 operates from a single 3.3V power  
supply and all inputs and outputs are fully TTL-  
compatible.  
4
Standby: 20 mW  
The PDM31532 is available in a 44-pin 400 mil plas-  
tic SOJ and a plastic TSOP (II) package for high-  
density surface assembly and is suitable for use in  
high-speed applications requiring high-speed  
storage.  
High-density 64K x 16 architecture  
3.3V (±0.3V) power supply  
Fully static operation  
TTL-compatible inputs and outputs  
Output buffer controls: OE  
Data byte controls: LB, UB  
Packages:  
5
6
Plastic SOJ (400 mil) - SO  
Plastic TSOP - T (II)  
Functional Block Diagram  
Vcc  
8
Vss  
Memory  
A8-A0  
Cell  
Array  
256 x 128 x 32  
32K x 32  
9
Data  
Input/  
Output  
Buffer  
I/O15-I/O0  
Sense Amp  
10  
11  
12  
Column  
Decoder  
WE  
OE  
UB  
LB  
Control  
Logic  
Column  
Address  
Buffer  
Clock  
Generator  
CE  
A15-A9  
Rev. 4.3 - 3/27/98  
1

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