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PDM31532LA20TTR PDF预览

PDM31532LA20TTR

更新时间: 2024-11-25 09:00:07
品牌 Logo 应用领域
IXYS 静态存储器光电二极管
页数 文件大小 规格书
9页 236K
描述
Standard SRAM, 64KX16, 20ns, CMOS, PDSO44, PLASTIC, TSOP2-44

PDM31532LA20TTR 数据手册

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PDM31532  
64K x 16 CMOS  
3.3V Static RAM  
1
2
Features  
Description  
High-speed access times  
- Com’l: 9, 10, 12, 15 and 20 ns  
- Ind: 12, 15 and 20 ns  
Low power operation (typical)  
- PDM31532LA  
The PDM31532 is a high-performance CMOS static  
RAM organized as 65,536 x 16 bits. The PDM31532  
features low power dissipation using chip enable  
(CE) and has an output enable input (OE) for fast  
memory access. Byte access is supported by upper  
and lower byte controls.  
3
Active: 200 mW  
Standby: 10 mW  
- PDM31532SA  
Active: 250 mW  
The PDM31532 operates from a single 3.3V power  
supply and all inputs and outputs are fully TTL-  
compatible.  
4
Standby: 20 mW  
The PDM31532 is available in a 44-pin 400 mil plas-  
tic SOJ and a plastic TSOP (II) package for high-  
density surface assembly and is suitable for use in  
high-speed applications requiring high-speed  
storage.  
High-density 64K x 16 architecture  
3.3V (±0.3V) power supply  
Fully static operation  
TTL-compatible inputs and outputs  
Output buffer controls: OE  
Data byte controls: LB, UB  
Packages:  
5
6
Plastic SOJ (400 mil) - SO  
Plastic TSOP - T (II)  
Functional Block Diagram  
Vcc  
8
Vss  
Memory  
A8-A0  
Cell  
Array  
256 x 128 x 32  
32K x 32  
9
Data  
Input/  
Output  
Buffer  
I/O15-I/O0  
Sense Amp  
10  
11  
12  
Column  
Decoder  
WE  
OE  
UB  
LB  
Control  
Logic  
Column  
Address  
Buffer  
Clock  
Generator  
CE  
A15-A9  
Rev. 4.3 - 3/27/98  
1

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