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PCZ33781EK/R2 PDF预览

PCZ33781EK/R2

更新时间: 2024-11-10 15:47:39
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管接口集成电路
页数 文件大小 规格书
44页 1326K
描述
SPECIALTY INTERFACE CIRCUIT, PDSO32, 0.65 PITCH, ROHS COMPLIANT, SOIC-32

PCZ33781EK/R2 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.65 PITCH, ROHS COMPLIANT, SOIC-32
针数:32Reach Compliance Code:unknown
风险等级:5.84Is Samacsys:N
接口集成电路类型:INTERFACE CIRCUITJESD-30 代码:R-PDSO-G32
JESD-609代码:e3长度:11 mm
湿度敏感等级:3功能数量:1
端子数量:32最高工作温度:90 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

PCZ33781EK/R2 数据手册

 浏览型号PCZ33781EK/R2的Datasheet PDF文件第2页浏览型号PCZ33781EK/R2的Datasheet PDF文件第3页浏览型号PCZ33781EK/R2的Datasheet PDF文件第4页浏览型号PCZ33781EK/R2的Datasheet PDF文件第5页浏览型号PCZ33781EK/R2的Datasheet PDF文件第6页浏览型号PCZ33781EK/R2的Datasheet PDF文件第7页 
Document Number: MC33781  
Rev. 4.0, 7/2008  
Freescale Semiconductor  
Advance Information  
Quad DSI 2.02 Master with  
Differential Drive and  
Frequency Spreading  
33781  
The 33781 is a master device for four differential DSI 2.02 buses.  
It contains the logic to interface the buses to a standard serial  
peripheral interface (SPI) port and the analog circuitry to drive data  
and power over the bus, as well as receive data from the remote slave  
devices.  
DIFFERENTIAL DSI 2.02 MASTER  
The differential mode of the 33781 generates lower  
electromagnetic interference (EMI) in situations where data rates and  
wiring make this a problem. Frequency spreading further reduces  
interference by spreading the energy across many frequencies,  
reducing the energy in any single frequency.  
EK SUFFIX (PB-FREE)  
98ASA10556D  
32-PIN SOICW EP  
Features  
• Four independent differential DSI (DBUS) channels  
• Dual SPI interface  
ORDERING INFORMATION  
Temperature  
• Enhanced bus fault performance  
• Automatic message cyclical redundancy checking (CRC)  
generation and checking for each channel  
• Enhanced register set with addressable buffer allows queuing of 4  
independent slave commands at one time for each channel  
• 8- to 16-Bit messages with 0- to 8-Bit CRC  
• Independent frequency spreading for each channel  
• Pseudo bus switch feature on channel 0  
• Pb-free packaging designated by suffix code EK  
Device  
Package  
Range (T )  
A
PCZ33781EK/R2  
-40°C to 90°C  
32 SOICW EP  
+5.0V  
+25V  
33781  
VCC  
SCLK  
CS  
VCC  
VSUP1  
DPH  
DPL  
D0H  
D0L  
1.0μF  
DBUS SLAVE  
SCLK0  
CS0  
DBUS SLAVE  
DBUS SLAVE  
DBUS SLAVE  
DBUS SLAVE  
MCU1  
MOSI  
MISO  
RST  
MOSI0  
MISO0  
RST  
D1H  
D1L  
CLK  
CLK  
GND  
D2H  
D2L  
VDD  
0.1μF  
VSS_IDDQ  
SCLK1  
D3H  
D3L  
SCLK1  
MISO1  
CS1  
MISO1  
MCU2  
CS1  
AGND GND  
VSS  
2.2nF capacitors from DOH, D0L,  
D1H, D1L, D2H, D2L, D3H and D3L  
to circuit ground are required for  
proper operation  
GND  
Figure 1. 33781 Simplified Application Diagram  
* This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2007-2008. All rights reserved.  

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