Datasheet > PCA9549BS

PCA9549BS

更新时间： 2024-11-07 04:54:07

品牌	Logo	应用领域
恩智浦 - NXP		开关
页数	文件大小	规格书
24页	136K
描述
Octal bus switch with individually I2C-bus controlled enables

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PCA9549BS 数据手册

PCA9549

Octal bus switch with individually I²C-bus controlled enables

Rev. 01 — 11 July 2006

Product data sheet

1. General description

The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled

by the I²C-bus. The low ON-state resistance of the switch allows connections to be made

with minimal propagation delay. Any individual A to B channel or combination of channels

can be selected via the I²C-bus, determined by the contents of the programmable Control

Port A to Port B, or vice versa. When the I²C-bus bit is LOW (logic 0), the switch is open,

creating a high-impedance state between the two ports, which stops the data ﬂow.

An active LOW reset input (RESET) allows the PCA9549 to recover from a situation

where the I²C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus

state machine and causes all the bits to be open, as does the internal power-on reset

function.

Three address pins allow up to eight devices on the same bus.

2. Features

I 8-bit bus switch (CBT)

I 5 Ω switch connection between two ports

I I²C-bus interface logic; compatible with SMBus standards

I Active LOW RESET input

I 3 address pins allowing up to 8 devices on the I²C-bus

I Bit selection via I²C-bus, in any combination

I Power-up with all bits deselected

I Low R_onswitches

I No glitch on power-up

I Supports hot insertion

I Low standby current

I Operating power supply voltage range of 2.3 V to 5.5 V

I 5 V tolerant inputs

I 0 Hz to 400 kHz clock frequency

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

I Packages offered: SO24, TSSOP24, HVQFN24

12 3 4 5 6 7...24

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