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PCA9545APW2 PDF预览

PCA9545APW2

更新时间: 2024-11-09 21:19:47
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
28页 154K
描述
IC,BUS CONTROLLER,TSSOP,20PIN

PCA9545APW2 技术参数

生命周期:Obsolete包装说明:TSSOP,
Reach Compliance Code:compliant风险等级:5.36
其他特性:ALSO OPERATES WITH 4.5 TO 5.5V SUPPLY系列:9545
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm逻辑集成电路类型:MULTIPLEXER
功能数量:1输入次数:4
输出次数:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-DRAIN输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):0.3 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

PCA9545APW2 数据手册

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PCA9545A  
4-channel I2C-bus switch with interrupt logic and reset  
Rev. 04 — 25 September 2006  
Product data sheet  
1. General description  
The PCA9545A is a quad bidirectional translating switch controlled via the I2C-bus. The  
SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual  
SCx/SDx channel or combination of channels can be selected, determined by the  
contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for  
each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of  
the four interrupt inputs.  
An active LOW reset input allows the PCA9545A to recover from a situation where one of  
the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the  
I2C-bus state machine and causes all the channels to be deselected as does the internal  
power-on reset function.  
The pass gates of the switches are constructed such that the VDD pin can be used to limit  
the maximum high voltage which will be passed by the PCA9545A. This allows the use of  
different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate  
with 5 V parts without any additional protection. External pull-up resistors pull the bus up  
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.  
2. Features  
I 1-of-4 bidirectional translating switches  
I I2C-bus interface logic; compatible with SMBus standards  
I 4 active LOW interrupt inputs  
I Active LOW interrupt output  
I Active LOW reset input  
I 2 address pins allowing up to 4 devices on the I2C-bus  
I Alternate address versions 1 and 2 allow up to a total of 12 devices on the bus for  
larger systems or to resolve address conflicts  
I Channel selection via I2C-bus, in any combination  
I Power-up with all switch channels deselected  
I Low Ron switches  
I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses  
I No glitch on power-up  
I Supports hot insertion  
I Low stand-by current  
I Operating power supply voltage range of 2.3 V to 5.5 V  
I 5 V tolerant Inputs  
I 0 Hz to 400 kHz clock frequency  

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