Datasheet > PCA9502BS,128

PCA9502BS,128

更新时间： 2024-01-29 01:57:46

品牌	Logo	应用领域
恩智浦 - NXP		PC 外围集成电路
页数	文件大小	规格书
27页	286K
描述
PCA9502 - 8-bit I/O expander with I2C-bus/SPI interface QFN 24-Pin

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PCA9502BS,128 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	QFN	包装说明：	HVQCCN, LCC24,.16SQ,20
针数：	24	Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01	风险等级：	1.14
Is Samacsys：	N	其他特性：	IT ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码：	S-PQCC-N24	JESD-609代码：	e4
长度：	4 mm	湿度敏感等级：	1
位数：	8	I/O 线路数量：	8
端口数量：	1	端子数量：	24
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装等效代码：	LCC24,.16SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	2.5/3.3 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	Parallel IO Port
最大供电电压：	2.7 V	最小供电电压：	2.3 V
标称供电电压：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	NICKEL PALLADIUM GOLD	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	4 mm
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE	Base Number Matches：	1

PCA9502BS,128 数据手册

PCA9502

NXP Semiconductors

8-bit I/O expander with I²C-bus/SPI interface

acknowledgement signal

from receiver

SDA

MSB

SCL

2 to 7

ACK

START

condition

STOP

condition

byte complete,

interrupt within receiver

clock line held LOW

while interrupt is serviced

002aab012

Fig 6. Data transfer on the I²C-bus

data output

by transmitter

transmitter stays off of the bus

during the acknowledge clock

data output

by receiver

acknowledgement signal

from receiver

SCL from master

002aab013

START

condition

Fig 7. Acknowledge on the I²C-bus

A slave receiver must generate an acknowledge after the reception of each byte, and a

master must generate one after the reception of each byte clocked out of the slave

transmitter.

There is an exception to the ‘acknowledge after every byte’ rule. It occurs when a master

is a receiver: it must signal an end of data to the transmitter by not signalling an

acknowledge on the last byte that has been clocked out of the slave. The acknowledge

related clock, generated by the master should still take place, but the SDA line will not be

pulled down. In order to indicate that this is an active and intentional lack of

acknowledgement, we shall term this special condition as a ‘negative acknowledge’.

9.2 Addressing and transfer formats

Each device on the bus has its own unique address. Before any data is transmitted on the

bus, the master transmits on the bus the address of the slave to be accessed for this

transaction. A well-behaved slave with a matching address, if it exists on the network,

should of course acknowledge the master's addressing. The addressing is done by the

first byte transmitted by the master after the START condition.

An address on the network is seven bits long, appearing as the most significant bits of the

address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is

transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete

data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is

shown in Figure 8.

PCA9502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 23 February 2016

8 of 27

1...5 6 789 10 11...27

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