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PCA9502BS,128

更新时间： 2024-02-26 02:01:08
品牌 Logo 应用领域
恩智浦 - NXP PC外围集成电路
页数 文件大小 规格书
27页 286K
描述
PCA9502 - 8-bit I/O expander with I2C-bus/SPI interface QFN 24-Pin

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PCA9502BS,128 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC24,.16SQ,20
针数：24Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：1.14
Is Samacsys：N其他特性：IT ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码：S-PQCC-N24JESD-609代码：e4
长度：4 mm湿度敏感等级：1
位数：8I/O 线路数量：8
端口数量：1端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：2.5/3.3 V认证状态：Not Qualified
座面最大高度：1 mm子类别：Parallel IO Port
最大供电电压：2.7 V最小供电电压：2.3 V
标称供电电压：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：4 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA9502BS,128 数据手册

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PCA9502  
NXP Semiconductors  
8-bit I/O expander with I2C-bus/SPI interface  
7.2 Interrupts  
The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna)  
enables interrupts due to I/O pin change of state, and the IRQ signal in response to an  
interrupt generation.  
8. Register descriptions  
The programming combinations for register selection are shown in Table 5.  
Table 5. Register map - read/write properties  
Register name  
IODir  
Read mode  
Write mode  
I/O pin direction  
I/O pin states  
I/O pin direction  
n/a  
IOState  
IOIntEna  
IOControl  
I/O interrupt enable register  
I/O pins control  
I/O interrupt enable register  
I/O pins control  
Table 6.  
PCA9502 internal registers  
Register  
address  
Register Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
General Register Set  
0x0A[1]  
0x0B[1]  
0x0C[1]  
0x0D[1]  
IODir  
bit 7  
bit 7  
bit 6  
bit 6  
bit 6  
bit 5  
bit 5  
bit 5  
bit 4  
bit 4  
bit 4  
bit 3  
bit 3  
bit 3  
bit 2  
bit 2  
bit 2  
bit 1  
bit 1  
bit 1  
bit 0  
bit 0  
bit 0  
R/W  
R/W  
R/W  
IOState  
IOIntEna bit 7  
reserved reserved reserved reserved reserved reserved reserved reserved reserved  
[2]  
[2]  
[2]  
[2]  
[2]  
[2]  
[2]  
[2]  
[2]  
0x0E[1]  
IOControl reserved reserved reserved reserved SReset  
reserved reserved IOLatch  
R/W  
[2]  
[2]  
[2]  
[2]  
[2]  
[2]  
[1] Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write).  
[2] These bits are reserved and should be set to 0.  
8.1 Programmable I/O pins Direction register (IODir)  
This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to  
GPIO7.  
Table 7.  
Bit  
IODir register (address 0x0A) bit description  
Symbol  
Description  
7:0  
IODir  
set GPIO pins 7:0 to input or output  
0 = input  
1 = output  
Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending  
interrupt will be cleared, that is, the interrupt signal will be negated.  
PCA9502  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2016. All rights reserved.  
Product data sheet  
Rev. 4 — 23 February 2016  
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