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PCA8574ATS,112

更新时间： 2024-01-02 02:34:28
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管外围集成电路
页数 文件大小 规格书
32页 1030K
描述
PCA8574/74A - Remote 8-bit I/O expander for I²C-bus with interrupt SSOP2 20-Pin

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PCA8574ATS,112 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP2包装说明：LSSOP, SSOP20,.25
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.29
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm湿度敏感等级：1
位数：8I/O 线路数量：8
端口数量：1端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：SSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：1.5 mm子类别：Parallel IO Ports
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA8574ATS,112 数据手册

 浏览型号PCA8574ATS,112的Datasheet PDF文件第7页浏览型号PCA8574ATS,112的Datasheet PDF文件第8页浏览型号PCA8574ATS,112的Datasheet PDF文件第9页浏览型号PCA8574ATS,112的Datasheet PDF文件第11页浏览型号PCA8574ATS,112的Datasheet PDF文件第12页浏览型号PCA8574ATS,112的Datasheet PDF文件第13页 
PCA8574; PCA8574A  
NXP Semiconductors  
Remote 8-bit I/O expander for I2C-bus with interrupt  
8.4 Power-on reset  
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA8574;  
PCA8574A in a reset condition until VDD has reached VPOR. At that point, the reset  
condition is released and the PCA8574; PCA8574A registers and I2C-bus/SMBus state  
machine will initialize to their default states of all I/Os to inputs with weak current source to  
V
DD. Thereafter VDD must be lowered below VPOR and back up to the operation voltage for  
power-on reset cycle.  
8.5 Interrupt output (INT)  
The PCA8574/74A provides an open-drain output (INT) which can be fed to a  
corresponding input of the microcontroller (see Figure 10). As soon as a port input is  
changed, the INT will be active (LOW) and notify the microcontroller.  
An interrupt is generated at any rising or falling edge of the port inputs. After time tv(Q), the  
signal INT is valid.  
The interrupt will reset to HIGH when data on the port is changed to the original setting or  
data is read or written by the master.  
In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the  
acknowledge bit of the data byte and also on the rising edge of the write to port pulse. The  
interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see  
Figure 8).  
The interrupt is reset (HIGH) in the Read mode on the rising edge of the acknowledge of  
slave address byte and on the rising edge of the read from port pulse (see Figure 9).  
During the interrupt reset, any I/O change close to the read or write pulse may not  
generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is  
reset, any change in I/Os will be detected and transmitted as an INT.  
At power-on reset all ports are in Input mode and the initial state of the ports is HIGH,  
therefore, for any port pin that is pulled LOW or driven LOW by external source, the  
interrupt output will be active (output LOW).  
V
DD  
device 1  
device 2  
device 16  
PCA8574  
PCA8574  
PCA8574A  
MICROCONTROLLER  
INT  
INT  
INT  
INT  
002aac682  
Fig 10. Application of multiple PCA8574/74As with interrupt  
PCA8574_PCA8574A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 3 June 2013  
10 of 32  
 
 
 
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