Datasheet > PCA8574ATS,112

PCA8574ATS,112

更新时间： 2024-01-16 14:57:32

品牌	Logo	应用领域
恩智浦 - NXP		PC 光电二极管外围集成电路
页数	文件大小	规格书
32页	1030K
描述
PCA8574/74A - Remote 8-bit I/O expander for I²C-bus with interrupt SSOP2 20-Pin

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PCA8574ATS,112 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SSOP2	包装说明：	LSSOP, SSOP20,.25
针数：	20	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.29
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e4
长度：	6.5 mm	湿度敏感等级：	1
位数：	8	I/O 线路数量：	8
端口数量：	1	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LSSOP
封装等效代码：	SSOP20,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	2.5/5 V	认证状态：	Not Qualified
座面最大高度：	1.5 mm	子类别：	Parallel IO Ports
最大供电电压：	5.5 V	最小供电电压：	2.3 V
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	4.4 mm
uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE	Base Number Matches：	1

PCA8574ATS,112 数据手册

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

8. I/O programming

8.1 Quasi-bidirectional I/Os

A quasi-bidirectional I/O is an input or output port without using a direction control register.

Whenever the master reads the register, the value returned to master depends on the

actual voltage or status of the pin. At power-on, all the ports are HIGH with a weak 100 A

internal pull-up to V_DD, but can be driven LOW by an internal transistor, or an external

signal. The I/O ports are entirely independent of each other, but each I/O octal is

controlled by the same read or write data byte.

Advantages of the quasi-bidirectional I/O over totem pole I/O include:

• Better for driving LEDs since the p-channel (transistor to V_DD) is small, which saves

die size and therefore cost. LED drive only requires an internal transistor to ground,

while the LED is connected to V_DDthrough a current-limiting resistor. Totem pole I/O

have both n-channel and p-channel transistors, which allow solid HIGH and LOW

output levels without a pull-up resistor — good for logic levels.

• Simpler architecture — only a single register and the I/O can be both input and output

at the same time. Totem pole I/O have a direction register that specifies the port pin

direction and it is always in that configuration unless the direction is explicitly

changed.

• Does not require a command byte. The simplicity of one register (no need for the

pointer register or, technically, the command byte) is an advantage in some

embedded systems where every byte counts because of memory or bandwidth

limitations.

There is only one register to control four possibilities of the port pin: Input HIGH, input

LOW, output HIGH, or output LOW.

Input HIGH: The master needs to write 1 to the register to set the port as an input mode

if the device is not in the default power-on condition. The master reads the register to

check the input status. If the external source pulls the port pin up to V_DDor drives

logic 1, then the master will read the value of 1.

Input LOW: The master needs to write 1 to the register to set the port to input mode if

the device is not in the default power-on condition. The master reads the register to

check the input status. If the external source pulls the port pin down to V_SSor drives

logic 0, which sinks the weak 100 A current source, then the master will read the value

of 0.

Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or

strong pull-up current when the master sets the port HIGH. The additional strong pull-up

is only active during the HIGH time of the acknowledge clock cycle. This accelerator

current helps the port’s 100 A current source make a faster rising edge into a heavily

loaded output, but only at the start of the acknowledge clock cycle to avoid bus

contention if an external signal is pulling the port LOW to V_SS/driving the port with

logic 0 at the same time. After the half clock cycle there is only the 100 A current

source to hold the port HIGH.

Output LOW: The master writes 0 to the register. There is a strong current sink

transistor that holds the port pin LOW. A large current may flow into the port, which

could potentially damage the part if the master writes a 0 to the register and an external

source is pulling the port HIGH at the same time.

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

7 of 32

1...4 5 678 9 10...32

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与PCA8574ATS,112相关器件

型号	品牌	描述	获取价格	数据表
PCA8574D	NXP	Remote 8-bit I/O expander for I2C-bus with interrupt	获取价格
PCA8574N	NXP	Remote 8-bit I/O expander for I2C-bus with interrupt	获取价格
PCA8574N,112	NXP	PCA8574/74A - Remote 8-bit I/O expander for I	获取价格
PCA8574PW	NXP	Remote 8-bit I/O expander for I2C-bus with interrupt	获取价格
PCA8574PW,112	NXP	PCA8574/74A - Remote 8-bit I/O expander for I	获取价格
PCA8574TS	NXP	Remote 8-bit I/O expander for I2C-bus with interrupt	获取价格

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