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PCA8574ATS,112 PDF预览

PCA8574ATS,112

更新时间: 2024-02-08 14:33:20
品牌 Logo 应用领域
恩智浦 - NXP PC光电二极管外围集成电路
页数 文件大小 规格书
32页 1030K
描述
PCA8574/74A - Remote 8-bit I/O expander for I²C-bus with interrupt SSOP2 20-Pin

PCA8574ATS,112 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP2包装说明:LSSOP, SSOP20,.25
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.29
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm湿度敏感等级:1
位数:8I/O 线路数量:8
端口数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:SSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:1.5 mm子类别:Parallel IO Ports
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA8574ATS,112 数据手册

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PCA8574; PCA8574A  
NXP Semiconductors  
Remote 8-bit I/O expander for I2C-bus with interrupt  
Simple code WRITE mode:  
<S> <slave address + write> <ACK> <data out> <ACK> <data out> <ACK> ...  
<data out> <ACK> <P>  
Remark: Bold type = generated by slave device.  
8.3 Reading from a port (Input mode)  
The port must have been previously written to logic 1, which is the condition after  
power-on reset. To enter the Read mode the master (microcontroller) addresses the slave  
device and sets the last bit of the address byte to logic 1 (address byte read). The slave  
will acknowledge and then send the data byte to the master. The master will NACK and  
then send the STOP condition or ACK and read the input register again.  
The read of any pin being used as an output will indicate HIGH or LOW depending on the  
actual state of the input pin.  
If the data on the input port changes faster than the master can read, this data may be  
lost. The DATA 2 and DATA 3 are lost because these data did not meet the setup time and  
hold time (see Figure 9).  
no acknowledge  
from master  
slave address  
data from port  
DATA 1  
data from port  
DATA 4  
SDA  
S
A6 A5 A4 A3 A2 A1 A0  
1
A
A
1
P
START condition  
R/W acknowledge  
from slave  
acknowledge  
from master  
STOP  
condition  
read from  
port  
DATA 2  
data at  
port  
DATA 1  
DATA 3  
DATA 4  
t
t
su(D)  
h(D)  
INT  
t
t
t
rst(INT)  
v(INT)  
rst(INT)  
002aah383  
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at  
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input  
data is lost.  
Fig 9. Read mode (input)  
Simple code for Read mode:  
<S> <slave address + read> <ACK> <data in> <ACK> ... <data in> <ACK> <data in>  
<NACK> <P>  
Remark: Bold type = generated by slave device.  
PCA8574_PCA8574A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2013. All rights reserved.  
Product data sheet  
Rev. 3 — 3 June 2013  
9 of 32  
 
 

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