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PAM1707BZKBA4

更新时间： 2024-09-21 05:59:31
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德州仪器 - TI 微处理器
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198页 1329K
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AM1707 ARM Microprocessor

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AM1707  
www.ti.com  
SPRS637A–FEBRUARY 2010–REVISED APRIL 2010  
AM1707 ARM Microprocessor  
Check for Samples: AM1707  
1 AM1707 ARM Microprocessor  
1.1 Features  
123  
– 32 Independent DMA Channels  
• Highlights  
– 8 Quick DMA Channels  
– Programmable Transfer Burst Size  
• 128K-Byte RAM Memory  
– 375/456-MHz ARM926EJ-S™ RISC Core  
– ARM9 Memory Architecture  
– Programmable Real-Time Unit Subsystem  
• 3.3V LVCMOS IOs (except for USB interfaces)  
• Two External Memory Interfaces:  
– EMIFA  
– Enhanced Direct-Memory-Access Controller  
3 (EDMA3)  
– Two External Memory Interfaces  
– Three Configurable 16550 type UART  
Modules  
– Two Serial Peripheral Interfaces (SPI)  
– Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
•
•
•
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
16-Bit SDRAM With 128MB Address  
Space  
– EMIFB  
32-Bit or 16-Bit SDRAM With 256MB  
Address Space  
– Two Master/Slave Inter-Integrated Circuit  
– USB 2.0 OTG Port With Integrated PHY  
– Three Multichannel Audio Serial Ports  
– 10/100 Mb/s Ethernet MAC (EMAC)  
– One 64-Bit General-Purpose Timer  
– One 64-bit General-Purpose/Watchdog Timer  
– Three Enhanced Pulse Width Modulators  
– Three 32-Bit Enhanced Capture Modules  
• Applications  
•
• Three Configurable 16550 type UART Modules:  
– UART0 With Modem Control Signals  
– 16-byte FIFO  
– 16x or 13x Oversampling Option  
• LCD Controller  
• Two Serial Peripheral Interfaces (SPI) Each  
With One Chip-Select  
• Programmable Real-Time Unit Subsystem  
(PRUSS)  
– Industrial Automation  
– Home Automation  
– Test and Measurement  
– Portable Data Terminals  
– Educational Consoles  
– Power Protection Systems  
– Two Independent Programmable Realtime  
Unit (PRU) Cores  
•
•
•
•
32-Bit Load/Store RISC architecture  
4K Byte instruction RAM per core  
512 Bytes data RAM per core  
PRU Subsystem (PRUSS) can be disabled  
via software to save power  
• 375/456-MHz ARM926EJ-S™ RISC Core  
– 32-Bit and 16-Bit (Thumb®) Instructions  
– Single Cycle MAC  
– Standard power management mechanism  
– ARM® Jazelle® Technology  
•
•
Clock gating  
Entire subsystem under a single PSC  
clock gating domain  
– EmbeddedICE-RT™ for Real-Time Debug  
• ARM9 Memory Architecture  
– 16K-Byte Instruction Cache  
– 16K-Byte Data Cache  
– 8K-Byte RAM (Vector Table)  
– 64K-Byte ROM  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
– Dedicated interrupt controller  
– Dedicated switched central resource  
• Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
• Two Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
– 2 Transfer Controllers  
• One Host-Port Interface (HPI) With 16-Bit-Wide  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited.  
ARM, Jazelle are registered trademarks of ARM Limited.  
ADVANCE INFORMATION concerns new products in the sampling  
or preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
Copyright © 2010, Texas Instruments Incorporated  
 
 
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