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PAM1707ZKBD4

更新时间： 2024-11-08 05:59:31
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德州仪器 - TI 微处理器
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155页 999K
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AM1705 ARM Microprocessor

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AM1705  
www.ti.com  
SPRS657A–FEBRUARY 2010–REVISED APRIL 2010  
AM1705 ARM Microprocessor  
Check for Samples: AM1705  
1 AM1705 ARM Microprocessor  
1.1 Features  
123  
– 32 Independent DMA Channels  
• Highlights  
– 8 Quick DMA Channels  
– Programmable Transfer Burst Size  
• 128K-Byte RAM Memory  
– 375/456-MHz ARM926EJ-S™ RISC Core  
– ARM9 Memory Architecture  
– Programmable Real-Time Unit Subsystem  
• 3.3V LVCMOS IOs (except for USB interface)  
• Two External Memory Interfaces:  
– EMIFA  
– Enhanced Direct-Memory-Access Controller  
3 (EDMA3)  
– Two External Memory Interfaces  
– Three Configurable 16550 type UART  
Modules  
•
•
NOR (8-/16-Bit-Wide Data)  
NAND (8-/16-Bit-Wide Data)  
– Two Serial Peripheral Interfaces (SPI)  
– Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
– EMIFB  
16-Bit SDRAM With 256MB Address  
Space  
•
– Two Master/Slave Inter-Integrated Circuit  
– USB 2.0 OTG Port With Integrated PHY  
– Two Multichannel Audio Serial Ports  
– 10/100 Mb/s Ethernet MAC (EMAC)  
– One 64-Bit General-Purpose Timer  
– One 64-bit General-Purpose/Watchdog Timer  
– Three Enhanced Pulse Width Modulators  
– Three 32-Bit Enhanced Capture Modules  
• Applications  
• Three Configurable 16550 type UART Modules:  
– UART0 With Modem Control Signals  
– 16-byte FIFO  
– 16x or 13x Oversampling Option  
• Two Serial Peripheral Interfaces (SPI) Each  
With One Chip-Select  
• Programmable Real-Time Unit Subsystem  
(PRUSS)  
– Two Independent Programmable Realtime  
Unit (PRU) Cores  
– Industrial Automation  
– Home Automation  
– Test and Measurement  
– Portable Data Terminals  
– Educational Consoles  
– Power Protection Systems  
•
•
•
•
32-Bit Load/Store RISC architecture  
4K Byte instruction RAM per core  
512 Bytes data RAM per core  
PRU Subsystem (PRUSS) can be disabled  
via software to save power  
– Standard power management mechanism  
• 375/456-MHz ARM926EJ-S™ RISC Core  
– 32-Bit and 16-Bit (Thumb®) Instructions  
– Single Cycle MAC  
•
•
Clock gating  
Entire subsystem under a single PSC  
clock gating domain  
– ARM® Jazelle® Technology  
– Dedicated interrupt controller  
– Dedicated switched central resource  
• Multimedia Card (MMC)/Secure Digital (SD)  
Card Interface with Secure Data I/O (SDIO)  
• Two Master/Slave Inter-Integrated Circuit (I2C  
Bus™)  
• USB 2.0 OTG Port With Integrated PHY (USB0)  
– USB 2.0 High-/Full-Speed Client  
– USB 2.0 High-/Full-/Low-Speed Host  
– End Point 0 (Control)  
– EmbeddedICE-RT™ for Real-Time Debug  
• ARM9 Memory Architecture  
– 16K-Byte Instruction Cache  
– 16K-Byte Data Cache  
– 8K-Byte RAM (Vector Table)  
– 64K-Byte ROM  
• Enhanced Direct-Memory-Access Controller 3  
(EDMA3):  
– 2 Transfer Controllers  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited.  
ARM, Jazelle are registered trademarks of ARM Limited.  
ADVANCE INFORMATION concerns new products in the sampling  
or preproduction phase of development. Characteristic data and other  
specifications are subject to change without notice.  
Copyright © 2010, Texas Instruments Incorporated  
 
 
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