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PALCE26V12H-10PI PDF预览

PALCE26V12H-10PI

更新时间: 2024-11-09 22:11:15
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超微 - AMD /
页数 文件大小 规格书
21页 213K
描述
28-Pin EE CMOS Versatile PAL Device

PALCE26V12H-10PI 数据手册

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FINAL  
COM’L: H-7/10/15/20  
IND: H-10/15/20  
PALCE26V12 Family  
28-Pin EE CMOS Versatile PAL Device  
DISTINCTIVE CHARACTERISTICS  
28-pin versatile PAL programmable logic  
Two clock inputs for independent functions  
device architecture  
Global asynchronous reset and synchronous  
Electrically erasable CMOS technology  
provides half power (only 115 mA) at high  
speed (7.5 ns propagation delay)  
preset for initialization  
Register preload for testability and built-in  
register reset on power-up  
14 dedicated inputs and 12 input/output  
Space-efficient 28-pin SKINNYDIP and PLCC  
macrocells for architectural flexibility  
packages  
Macrocells can be registered or combinatorial,  
Center VCC and GND pins to improve signal  
and active high or active low  
characteristics  
Varied product term distribution allows up to  
Extensive third-party software and programmer  
16 product terms per output  
support through FusionPLD partners  
GENERAL DESCRIPTION  
The PALCE26V12 is a 28-pin version of the popular  
PAL22V10 architecture. Built with low-power, high-  
speed, electrically-erasable CMOS technology, the  
PALCE26V12 offers many unique advantages.  
The product terms are connected to the fixed OR array  
with a varied distribution from 8 to 16 across the outputs  
(see Block Diagram). The OR sum of the products feeds  
the output macrocell. Each macrocell can be pro-  
grammed as registered or combinatorial, active high or  
active low, with registered I/O possible. The flip-flop can  
be clocked by one of two clock inputs. The output  
configuration is determined by four bits controlling three  
multiplexers in each macrocell.  
Device logic is automatically configured according to  
the user’s design specification. Design is simplified by  
design software, allowing automatic creation of a  
programming file based on Boolean or state equations.  
The software can also be used to verify the design and  
can provide test vectors for the programmed device.  
AMD’s FusionPLD program allows PALCE26V12  
designs to be implemented using a wide variety of  
popular industry-standard design tools. By working  
closely with the FusionPLD partners, AMD certifies that  
the tools provide accurate, quality support. By ensuring  
that third-party tools are available, costs are lowered  
because a designer does not have to buy a complete set  
of new tools for each device. The FusionPLD program  
also greatly reduces design time since a designer can  
use a tool that is already installed and familiar. Please  
refer to the PLD Software Reference Guide for certified  
development systems and the Programmer Reference  
Guide for approved programmers.  
The PALCE26V12 utilizes the familiar sum-of-products  
(AND/OR) architecture that allows users to implement  
complex logic functions easily and efficiently. Multiple  
levels of combinatorial logic can always be reduced  
to sum-of-products form, taking advantage of the  
very wide input gates available in PAL devices. The  
functions are programmed into the device through  
electrically-erasable floating-gate cells in the AND logic  
array and the macrocells. In the unprogrammed state,  
all AND product terms float HIGH. If both true and  
complement of any input are connected, the term will be  
permanently LOW.  
Publication# 16072 Rev. E Amendment/0  
Issue Date: February 1996  
2-306  

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