5秒后页面跳转
捷配首页

Datasheet > PALCE22V10H-10SC/5
PALCE22V10H-10SC/5 PDF预览

PALCE22V10H-10SC/5

更新时间： 2024-11-09 22:07:31
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑光电二极管输入元件时钟
页数 文件大小 规格书
34页 662K
描述
24-Pin EE CMOS (Zero Power) Versatile PAL Device

阅读下载

中文翻译

获取价格

PALCE22V10H-10SC/5 数据手册

 浏览型号PALCE22V10H-10SC/5的Datasheet PDF文件第2页浏览型号PALCE22V10H-10SC/5的Datasheet PDF文件第3页浏览型号PALCE22V10H-10SC/5的Datasheet PDF文件第4页浏览型号PALCE22V10H-10SC/5的Datasheet PDF文件第5页浏览型号PALCE22V10H-10SC/5的Datasheet PDF文件第6页浏览型号PALCE22V10H-10SC/5的Datasheet PDF文件第7页 
PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25  
PALCE22V10Z COM'L: -25 IND: -15/25  
PALCE22V10 and PALCE22V10Z  
Families  
24-Pin EE CMOS (Zero Power) Versatile PAL Device  
DISTINCTIVE CHARACTERISTICS  
  As fast as 5-ns propagation delay and 142.8 MHz f  
  Low -pow er EE CMOS  
(external)  
MAX  
  10 macrocells programmable as registered or combinatorial, and active high or active low to  
match application needs  
  Varied product term distribution allow s up to 16 product terms per output for complex  
functions  
  Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)  
  Global asynchronous reset and synchronous preset for initialization  
  Pow er-up reset for initialization and register preload for testability  
  Extensive third-party softw are and programmer support  
  24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC  
  5-ns and 7.5-ns versions utilize split leadframes for improved performance  
GENERAL DESCRIPTION  
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and  
flip-flops at a reduced chip count.  
®
The PALCE22V10Z is an advanced PAL device built with zero-power, high-speed, electrically-  
erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-  
power CMOS SSI/MSI gates and flip-flops at a reduced chip count.  
The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby  
current, the PALCE22V10Z allows battery-powered operation for an extended period.  
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The  
PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed  
to create custom product terms, while the OR array sums selected terms at the outputs.  
The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across  
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each  
macrocell can be programmed as registered or combinatorial, and active-high or active low. The  
output configuration is determined by two bits controlling two multiplexers in each macrocell.  
Publication# 1 6564  
Amendment/0  
Rev: E  
Issue Date: November 1 998  
1234567...34

中文翻译

下载PDF

与PALCE22V10H-10SC/5相关器件

型号 品牌 获取价格 描述 数据表
PALCE22V10H-10SI LATTICE

获取价格

 		EE PLD, 10ns, CMOS, PDSO24,
PALCE22V10H-10SI/4 LATTICE

获取价格

 		EE PLD, 10ns, CMOS, PDSO24,
PALCE22V10H10ZC/5 ETC

获取价格

 		ASIC
PALCE22V10H-15/B3A ETC

获取价格

 		Electrically-Erasable PLD
PALCE22V10H-15/BKA ETC

获取价格

 		Electrically-Erasable PLD
PALCE22V10H-15/BLA ETC

获取价格

 		Electrically-Erasable PLD
PALCE22V10H-15DC ETC

获取价格

 		Electrically-Erasable PLD
PALCE22V10H15DC/4 ETC

获取价格

 		ASIC
PALCE22V10H-15E4/B3A ETC

获取价格

 		Electrically-Erasable PLD
PALCE22V10H-15E4/BKA ETC

获取价格

 		Electrically-Erasable PLD

与PALCE22V10H-10SC/5相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证