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PALCE22V10H-15PC/4 PDF预览

PALCE22V10H-15PC/4

更新时间： 2024-11-07 22:26:51
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
34页 662K
描述
24-Pin EE CMOS (Zero Power) Versatile PAL Device

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中文翻译

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PALCE22V10H-15PC/4 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：0.300 INCH, SKINNY, PLASTIC, DIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.08Is Samacsys：N
其他特性：10 MACROCELLS, 1 EXTERNAL CLOCK, SHARED INPUT/CLOCK, VARIABLE PRODUCT TERMS架构：PAL-TYPE
最大时钟频率：50 MHzJESD-30 代码：R-PDIP-T24
JESD-609代码：e0长度：30.734 mm
专用输入次数：11I/O 线路数量：10
输入次数：22输出次数：10
产品条款数：132端子数量：24
最高工作温度：75 °C最低工作温度：
组织：11 DEDICATED INPUTS, 10 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V可编程逻辑类型：EE PLD
传播延迟：15 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子面层：Tin/Lead (Sn85Pb15)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

PALCE22V10H-15PC/4 数据手册

 浏览型号PALCE22V10H-15PC/4的Datasheet PDF文件第2页浏览型号PALCE22V10H-15PC/4的Datasheet PDF文件第3页浏览型号PALCE22V10H-15PC/4的Datasheet PDF文件第4页浏览型号PALCE22V10H-15PC/4的Datasheet PDF文件第5页浏览型号PALCE22V10H-15PC/4的Datasheet PDF文件第6页浏览型号PALCE22V10H-15PC/4的Datasheet PDF文件第7页 
PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25  
PALCE22V10Z COM'L: -25 IND: -15/25  
PALCE22V10 and PALCE22V10Z  
Families  
24-Pin EE CMOS (Zero Power) Versatile PAL Device  
DISTINCTIVE CHARACTERISTICS  
  As fast as 5-ns propagation delay and 142.8 MHz f  
  Low -pow er EE CMOS  
(external)  
MAX  
  10 macrocells programmable as registered or combinatorial, and active high or active low to  
match application needs  
  Varied product term distribution allow s up to 16 product terms per output for complex  
functions  
  Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)  
  Global asynchronous reset and synchronous preset for initialization  
  Pow er-up reset for initialization and register preload for testability  
  Extensive third-party softw are and programmer support  
  24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC  
  5-ns and 7.5-ns versions utilize split leadframes for improved performance  
GENERAL DESCRIPTION  
The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and  
flip-flops at a reduced chip count.  
®
The PALCE22V10Z is an advanced PAL device built with zero-power, high-speed, electrically-  
erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-  
power CMOS SSI/MSI gates and flip-flops at a reduced chip count.  
The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby  
current, the PALCE22V10Z allows battery-powered operation for an extended period.  
The PAL device implements the familiar Boolean logic transfer function, the sum of products. The  
PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed  
to create custom product terms, while the OR array sums selected terms at the outputs.  
The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across  
the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each  
macrocell can be programmed as registered or combinatorial, and active-high or active low. The  
output configuration is determined by two bits controlling two multiplexers in each macrocell.  
Publication# 1 6564  
Amendment/0  
Rev: E  
Issue Date: November 1 998  
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中文翻译

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PALCE22V10H-15PC/4 替代型号

型号 品牌 替代类型 描述 数据表
GAL22V10D-15LPN LATTICE

完全替代

 All Devices Discontinued
GAL22V10D-15QPN LATTICE

完全替代

 All Devices Discontinued
GAL22V10D-15LP LATTICE

完全替代

 High Performance E2CMOS PLD Generic Array Logic

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