AMD
use the feedback path of MC7 and pin 11 will use the
feedback path of MC0.
Configuration Options
Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O, or dedicated input. In the registered output
configuration, theoutputbufferisenabledbytheOE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MC0 and MC7, a macrocell configured
as a dedicated input derives the input signal from an ad-
jacent I/O. MC0 derives its input from pin 11 (OE) and
MC7 from pin 1 (CLK).
Combinatorial I/O in a Non-Registered
Device
ThecontrolbitsettingsareSG0=1, SG1=1, andSL0x =
1. Only seven product terms are available to the OR
gate. The eighth product term is used to enable the out-
put buffer. The signal at the I/O pin is fed back to the
AND array via the feedback multiplexer. This allows the
pin to be used as an input.
Because CLK and OE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback path of MC7 and pin 11 will use the
feedback path of MC0.
The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL00 through SL07 and SL10
through SL17). SG0 determines whether registers will
be allowed. SG1 determines whether the PALCE16V8
will emulate a PAL16R8 family or a PAL10H8 family de-
vice. Within each macrocell, SL0x, in conjunction with
SG1, selects the configuration of the macrocell, and
SL1x sets the output as either active low or active high
for the individual macrocell.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
1. Only seven product terms are available to the OR
gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding I/O
signal.
Dedicated Input Configuration
The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0x are the control signals for all four multiplexers. In
MC0 and MC7, SG0 replaces SG1 on the feedback mul-
tiplexer. This accommodates CLK being the adjacent
pin for MC7 and OE the adjacent pin for MC0.
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
1. Theoutputbufferisdisabled. ExceptforMC0 andMC7
thefeedbacksignalisanadjacentI/O. ForMC0 and MC7
the feedback signals are pins 1 and 11. These configu-
rations are summarized in Table 1 and illustrated in
Figure 2.
Table 1. Macrocell Configuration
Registered Output Configuration
SG0 SG1 SL0X Cell Configuration Devices Emulated
Device Uses Registers
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1x. The flip-flop is
loaded on the LOW-to-HIGH transition of CLK. The
feedback path is from Q on the register. The output
buffer is enabled by OE.
0
1
0
Registered Output PAL16R8, 16R6,
16R4
Combinatorial I/O PAL16R6, 16R4
0
1
1
Device Uses No Registers
1
1
1
0
0
1
0
1
1
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
Input
Combinatorial Configurations
Combinatorial I/O PAL16L8
The PALCE16V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
Programmable Output Polarity
The polarity of each macrocell can be active-high or ac-
tive-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Dedicated Output in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
0. All eight product terms are available to the OR gate.
Although the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 15 and 16. Pins
15 and 16 do not use feedback in this mode. Because
CLK and OE are not used in a non-registered device,
pins 1 and 11 are available as input signals. Pin 1 will
Selection is through a programmable bit SL1x which
controls an exclusive-OR gate at the output of the AND/
OR logic. The output is active high if SL1x is 1 and active
low if SL1x is 0.
2-40
PALCE16V8 Family
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