Datasheet > PALCE16V8

PALCE16V8

更新时间： 2024-11-09 22:50:47

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
32页	611K
描述
EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic

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PALCE16V8 数据手册

PALCE16V8

COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25

IND:-12/15/25

PALCE16V8Z COM’L:-25

PALCE16V8 and PALCE16V8Z Families

EE CMOS (Zero-Power) 20-Pin Universal

Programmable Array Logic

DISTINCTIVE CHARACTERISTICS

Pin and function compatible w ith all 20-pin PAL devices

Electrically erasable CMOS technology provides reconﬁgurable logic and full testability

High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

Direct plug-in replacement for the PAL16R8 series

Outputs programmable as registered or combinatorial in any combination

Peripheral Component Interconnect (PCI) compliant

Programmable output polarity

Programmable enable/disable control

Preloadable output registers for testability

Automatic register reset on pow er up

Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages

Extensive third-party softw are and programmer support

Fully tested for 100% programming and functional yields and high reliability

5-ns version utilizes a split leadframe for improved performance

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-

erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The

macrocells provide a universal device architecture. The PALCE16V8 will directly replace the

PAL16R8, with the exception of the PAL16C1.

The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby

current, the PALCE16V8Z allows battery-powered operation for an extended period.

The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to

implement complex logic functions easily and efﬁciently. Multiple levels of combinatorial logic

can always be reduced to sum-of-products form, taking advantage of the very wide input gates

available in PAL devices. The equations are programmed into the device through ﬂoating-gate

cells in the AND logic array that can be erased electrically.

The ﬁxed OR array allows up to eight data product terms per output for logic functions. The

sum of these products feeds the output macrocell. Each macrocell can be programmed as

registered or combinatorial with an active-high or active-low output. The output conﬁguration

is determined by two global bits and one local bit controlling four multiplexers in each

macrocell.

Publication# 1 6493

Amendment/0

Rev: F

Issue Date: September 2000

12 3 4 5 6 7...32

中文翻译

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与PALCE16V8相关器件

型号	品牌	获取价格	描述	数据表
PALCE16V8 AND PALCE16V8Z FAMILIES	ETC	获取价格	EE CMOS (Zero-Power) 20-Pin Universal Programmable Array Logic
PALCE16V8-10	CYPRESS	获取价格	Flash-Erasable Reprogrammable CMOS PAL Device
PALCE16V8-10DMB	CYPRESS	获取价格	Flash-Erasable Reprogrammable CMOS PAL Device
PALCE16V8-10JC	CYPRESS	获取价格	Flash-Erasable Reprogrammable CMOS PAL Device
PALCE16V8-10JCT	CYPRESS	获取价格	暂无描述
PALCE16V8-10JI	CYPRESS	获取价格	Flash-Erasable Reprogrammable CMOS PAL Device
PALCE16V8-10JIR	CYPRESS	获取价格	Flash PLD, 10ns, CMOS, PQCC20, PLASTIC, LCC-20
PALCE16V8-10LMB	CYPRESS	获取价格	Flash-Erasable Reprogrammable CMOS PAL Device
PALCE16V8-10PC	CYPRESS	获取价格	Flash-Erasable Reprogrammable CMOS PAL Device
PALCE16V8-10PI	CYPRESS	获取价格	Flash-Erasable Reprogrammable CMOS PAL Device

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