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P89LPC912HDH PDF预览

P89LPC912HDH

更新时间： 2024-10-27 11:56:19
品牌 Logo 应用领域
恩智浦 - NXP 闪存微控制器和处理器外围集成电路光电二极管时钟
页数 文件大小 规格书
66页 313K
描述
8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM

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P89LPC912HDH 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：4.4 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14针数：14
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.84具有ADC：NO
其他特性：OPERATES AT 2.4V MINIMUM SUPPLY AT 12 MHZ地址总线宽度：
位大小：8CPU系列：8051
最大时钟频率：18 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：5 mm湿度敏感等级：1
I/O 线路数量：12端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not QualifiedRAM（字节）：128
ROM（单词）：1024ROM可编程性：FLASH
座面最大高度：1.1 mm速度：18 MHz
子类别：Microcontrollers最大压摆率：16 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：4.4 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

P89LPC912HDH 数据手册

 浏览型号P89LPC912HDH的Datasheet PDF文件第2页浏览型号P89LPC912HDH的Datasheet PDF文件第3页浏览型号P89LPC912HDH的Datasheet PDF文件第4页浏览型号P89LPC912HDH的Datasheet PDF文件第5页浏览型号P89LPC912HDH的Datasheet PDF文件第6页浏览型号P89LPC912HDH的Datasheet PDF文件第7页 
P89LPC912/913/914  
8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V  
flash with 128-byte RAM  
Rev. 05 — 28 September 2007  
Product data sheet  
1. General description  
The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages,  
based on a high performance processor architecture that executes instructions in two to  
four clocks, six times the rate of standard 80C51 devices. Many system-level functions  
have been incorporated into the P89LPC912/913/914 in order to reduce component  
count, board space, and system cost.  
2. Features  
2.1 Principal features  
I 1 kB byte-erasable flash code memory organized into 256 B sectors and 16 B pages.  
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.  
I 128 B RAM data memory.  
I Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon  
timer overflow or to become a PWM output.  
I 23-bit system timer that can also be used as a RTC.  
I Two analog comparators with selectable inputs and reference source.  
I Enhanced UART with fractional baud rate generator, break detect, framing error  
detection, automatic address detection and versatile interrupt capabilities  
(P89LPC913, P89LPC914).  
I SPI communication port.  
I Internal RC oscillator (factory calibrated to ±1 %) option allows operation without  
external oscillator components. The RC oscillator option is selectable and fine tunable.  
I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or  
driven to 5.5 V).  
I Up to 12 I/O pins when using internal oscillator and reset options.  
2.2 Additional features  
I 14-pin TSSOP packages.  
I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns  
for all instructions except multiply and divide when executing at 18 MHz (167 ns to  
333 ns at 12 MHz). This is six times the performance of the standard 80C51 running at  
the same clock frequency. A lower clock frequency for the same performance results in  
power savings and reduced EMI.  
I In-Application Programming (IAP-Lite) and byte erase allows code memory to be used  
for non-volatile data storage.  
1234567...66

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