Datasheet > P4C1024-45CJMB

P4C1024-45CJMB

更新时间： 2022-12-02 00:11:59

品牌	Logo	应用领域
PYRAMID		静态存储器
页数	文件大小	规格书
14页	923K
描述
Standard SRAM, 128KX8, 45ns, CMOS, CDSO32, CERAMIC, SOJ-32

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P4C1024-45CJMB 数据手册

P4C1024

TIMING WAVEFORM OF READ CꢁCLE NO. 1 (OE CONTROLLED)⁽⁵⁾

TIMING WAVEFORM OF READ CꢁCLE NO. 2 (ADDRESS CONTROLLED)^(5,6)

TIMING WAVEFORM OF READ CꢁCLE NO. 3 (CE₁, CE₂CONTROLLED)^(5,7,10)

Notes:

5. WE is HIGH for READ cycle.

9. READ Cycle Time is measured from the last valid address to the ﬁrst

transitioning address.

10. Transitions caused by a chip enable control have similar delays

irrespective of whether CE₁or CE₂causes them.

6. CE₁is LOW, CE₂is HIGH and OE is LOW for READ cycle.

7. ADDRESS must be valid prior to, or coincident with CE₁transition

LOW and CE₂transition HIGH.

8. Transition is measured ± 200 mV from steady state voltage prior

to change, with loading as speciﬁed in Figure 1. This parameter is

sampled and not 100% tested.

Document # SRAM124 REV C

Page 5 of 14

1 2 3 456 7 8...14

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