5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 现场可编程门阵列> ORSO42G5-1BMN484C
ORSO42G5-1BMN484C PDF预览

ORSO42G5-1BMN484C

更新时间： 2024-11-05 02:56:51
品牌 Logo 应用领域
莱迪思 - LATTICE 现场可编程门阵列可编程逻辑
页数 文件大小 规格书
153页 1628K
描述
0.6 to 2.7 Gbps SONET Backplane Interface FPSCs

阅读下载

中文翻译

获取价格

ORSO42G5-1BMN484C 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：LEAD FREE, FPBGA-484
针数：484Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.82JESD-30 代码：S-XBGA-B484
JESD-609代码：e1湿度敏感等级：3
可配置逻辑块数量：1226等效关口数量：333000
端子数量：484最高工作温度：125 °C
最低工作温度：-40 °C组织：1226 CLBS, 333000 GATES
封装主体材料：UNSPECIFIED封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子位置：BOTTOM
Base Number Matches：1

ORSO42G5-1BMN484C 数据手册

 浏览型号ORSO42G5-1BMN484C的Datasheet PDF文件第2页浏览型号ORSO42G5-1BMN484C的Datasheet PDF文件第3页浏览型号ORSO42G5-1BMN484C的Datasheet PDF文件第4页浏览型号ORSO42G5-1BMN484C的Datasheet PDF文件第5页浏览型号ORSO42G5-1BMN484C的Datasheet PDF文件第6页浏览型号ORSO42G5-1BMN484C的Datasheet PDF文件第7页 
ORCA® ORSO42G5 and ORSO82G5  
0.6 to 2.7 Gbps SONET Backplane Interface FPSCs  
July 2008  
Data Sheet DS1028  
Introduction  
Lattice has extended its family of high-speed serial backplane devices with the ORSO42G5 and ORSO82G5  
devices. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSO42G5 and  
ORSO82G5 are high-speed transceivers with aggregate bandwidths of over 10 Gbps and 20 Gbps respectively.  
These devices are targeted toward users needing high-speed backplane interfaces for SONET and other non-  
SONET applications.The ORSO42G5 has four channels and the ORSO82G5 has eight channels of integrated 0.6-  
2.7Gbps SERDES channels with built-in Clock and Data Recovery (CDR), along with more than 400K usable  
FPGA system gates. The CDR circuitry, available from Lattice’s high-speed I/O portfolio (sysHSI™), has already  
been used in numerous applications to create STS-48/STM-16 and STS-192/STM-64 SONET/SDH interfaces.  
With the addition of protocol and access logic, such as framers and Packet-over-SONET (PoS) interfaces, design-  
ers can build a configurable interface using proven backplane driver/receiver technology. Designers can also use  
the device to drive high-speed data transfer across buses within a system that are not SONET/SDH based. The  
ORSO42G5 and ORSO82G5 can also be used to provide a full 10 Gbps backplane data connection and, with the  
ORSO82G5, support both work and protection connections between a line card and switch fabric.  
The ORSO42G5 and ORSO82G5 support a clockless high-speed interface for interdevice communication on a  
board or across a backplane. The built-in clock recovery of the ORSO42G5 and ORSO82G5 allows higher system  
performance, easier-to-design clock domains in a multiboard system and fewer signals on the backplane. Network  
designers will benefit from using the backplane transceiver as a network termination device. Sister devices, the  
ORT42G5 and the ORT82G5, support 8b/10b encoding/decoding and link state machines for 10 Gbit Ethernet  
(XAUI) and Fibre Channel. The ORSO42G5 and ORSO82G5 perform SONET data scrambling/descrambling,  
streamlined SONET framing, limited Transport OverHead (TOH) handling, plus the programmable logic to termi-  
nate the network into proprietary systems. The cell processing feature in the ORSO42G5 and ORSO82G5 makes  
them ideal for interfacing devices with any proprietary data format across a high-speed backplane. For non-SONET  
applications, all SONET functionality is hidden from the user and no prior networking knowledge is required. The  
ORSO42G5 and ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.  
Table 1. ORCA ORSO42G5 and ORSO82G5 Family – Available FPGA Logic  
FPGA  
PFU  
FPGA Max  
User I/O  
EBR  
EBR Bits  
(K)  
System  
Device  
ORSO42G5  
ORSO82G5  
PFU Rows Columns Total PFUs  
LUTs  
10,368  
10,368  
Blocks2  
Gates (K)1  
36  
36  
36  
36  
1296  
1296  
204  
372  
12  
12  
111  
111  
333-643  
333-643  
1. The embedded core, Embedded System Bus, FPGA interface and MPI are not included in the above gate counts. The System Gate  
ranges are derived from the following: Minimum System Gates assumes 100% of the PFUs are used for logic only (No PFU RAM) with  
40% EBR usage and 2 PLLs. Maximum System Gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80%  
EBR usage and 4 PLLs.  
2. There are two 4K x 36 (144K bits each) RAM blocks in the embedded core which are also accessible by the FPGA logic.  
.
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand  
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.  
www.latticesemi.com  
1
DS1028_08.0  
1234567...153

中文翻译

下载PDF

与ORSO42G5-1BMN484C相关器件

型号 品牌 获取价格 描述 数据表
ORSO42G5-1BMN484I LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO42G5-2BM484C LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO42G5-2BM484I LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO42G5-2BMN484C LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO42G5-2BMN484I LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO42G5-3BM484C LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO42G5-3BMN484C LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5 LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680I LATTICE

获取价格

 		0.6 to 2.7 Gbps SONET Backplane Interface FPSCs

与ORSO42G5-1BMN484C相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证