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OR4E02-2BM416C

更新时间： 2024-11-18 03:22:15
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
152页 2702K
描述
ORCASeries 4 FPGAs

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OR4E02-2BM416C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, FBGA-416
针数：416Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.85其他特性：MAXIMUM NO OF USABLE GATES IS 397000
最大时钟频率：420 MHzCLB-Max的组合延迟：0.81 ns
JESD-30 代码：S-PBGA-B416长度：27 mm
湿度敏感等级：3可配置逻辑块数量：624
等效关口数量：201000输入次数：290
逻辑单元数量：4992输出次数：290
端子数量：416最高工作温度：70 °C
最低工作温度：组织：624 CLBS, 201000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA416,26X26,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.5/3.3 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.38 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：27 mm

OR4E02-2BM416C 数据手册

 浏览型号OR4E02-2BM416C的Datasheet PDF文件第2页浏览型号OR4E02-2BM416C的Datasheet PDF文件第3页浏览型号OR4E02-2BM416C的Datasheet PDF文件第4页浏览型号OR4E02-2BM416C的Datasheet PDF文件第5页浏览型号OR4E02-2BM416C的Datasheet PDF文件第6页浏览型号OR4E02-2BM416C的Datasheet PDF文件第7页 
Data Sheet  
May, 2006  
®
ORCA Series 4 FPGAs  
■ Traditional I/O selections:  
— LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V)  
I/Os.  
Introduction  
Built on the Series 4 reconfigurable embedded sys-  
tem-on-a-chip (SoC) architecture, Lattice introduces  
its new family of generic Field-Programmable Gate  
Arrays (FPGAs). The high-performance and highly  
versatile architecture brings a new dimension to  
bringing network system designs to market in less  
time than ever before. This new device family offers  
many new features and architectural enhancements  
not available in any earlier FPGA generations. Bring-  
ing together highly flexible SRAM-based programma-  
ble logic, powerful system features, a rich hierarchy  
of routing and interconnect resources, and meeting  
multiple interface standards, the Series 4 FPGA  
accommodates the most complex and high-perfor-  
mance intellectual property (IP) network designs.  
— Per pin-selectable I/O clamping diodes provide  
3.3 V PCI compliance.  
— Individually programmable drive capability:  
24 mA sink/12 mA source, 12 mA sink/6 mA  
source, or 6 mA sink/3 mA source.  
— Two slew rates supported (fast and slew-lim-  
ited).  
— Fast-capture input latch and input flip-flop  
(FF)/latch for reduced input setup time and zero  
hold time.  
— Fast open-drain drive capability.  
— Capability to register 3-state enable signal.  
— Off-chip clock drive capability.  
— Two-input function generator in output path.  
■ New programmable high-speed I/O:  
— Single-ended: GTL, GTL+, PECL, SSTL3/2  
(class I and II), HSTL (Class I, III, and IV), ZBT,  
and DDR.  
— Double-ended: LDVS, bused-LVDS, and  
LVPECL. Programmable (on/off) internal parallel  
termination (100 Ω) also supported for these  
I/Os.  
Programmable Features  
■ High-performance platform design:  
— 0.16 μm 7-level metal technology.  
— Internal performance of >250 MHz.  
— I/O performance of >420 MHz.  
— Meets multiple I/O interface standards.  
— 1.5 V operation (30% less power than 1.8 V  
operation) translates to greater performance.  
Table 1. ORCA Series 4—Available FPGA Logic  
EBR  
Blocks  
EBR Bits  
(K)  
Usable*  
Gates (K)  
Device  
Rows  
Columns  
PFUs  
User I/O  
LUTs  
OR4E02  
OR4E04  
OR4E06  
26  
36  
46  
24  
36  
44  
624  
405  
466  
466  
4,992  
10,368  
16,192  
8
74  
201—397  
333—643  
471—899  
1,296  
2,024  
12  
16  
111  
148  
* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following:  
minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum  
system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.  
Note: Devices are not pinout compatible with ORCA Series 2/3.  
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All  
other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to  
change without notice.  
www.latticesemi.com  
1
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中文翻译

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OR4E02-2BM416C 替代型号

型号 品牌 替代类型 描述 数据表
OR4E04-2BM416C LATTICE

完全替代

 ORCASeries 4 FPGAs
OR4E04-2BA352C LATTICE

类似代替

 ORCASeries 4 FPGAs
OR4E02-2BA352C LATTICE

类似代替

 ORCASeries 4 FPGAs

与OR4E02-2BM416C相关器件

型号 品牌 获取价格 描述 数据表
OR4E022BM416-DB LATTICE

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 		Field Programmable Gate Array, 624 CLBs, 260000 Gates, 66MHz, 4992-Cell, CMOS, PBGA416, PL
OR4E02-2BM416I LATTICE

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 		ORCASeries 4 FPGAs
OR4E02-2BM680C LATTICE

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 		ORCASeries 4 FPGAs
OR4E022BM680-DB LATTICE

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 		Field Programmable Gate Array, 624 CLBs, 260000 Gates, 66MHz, 4992-Cell, CMOS, PBGA680, PL
OR4E02-2BM680I LATTICE

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 		ORCASeries 4 FPGAs
OR4E02-2BMN416C LATTICE

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 		Field Programmable Gate Array, 624 CLBs, 201000 Gates, 420MHz, CMOS, PBGA416, PLASTIC, FBG
OR4E02-2BMN416I LATTICE

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 		Field Programmable Gate Array, 624 CLBs, 201000 Gates, 420MHz, CMOS, PBGA416, PLASTIC, FBG
OR4E02-2BMN680C LATTICE

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 		Field Programmable Gate Array, 624 CLBs, 201000 Gates, 420MHz, CMOS, PBGA680, PLASTIC, FBG
OR4E02-3BA352C LATTICE

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 		ORCASeries 4 FPGAs
OR4E023BA352-DB LATTICE

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 		Field Programmable Gate Array, 624 CLBs, 260000 Gates, 66MHz, 4992-Cell, CMOS, PBGA352, PL

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