Datasheet > OR3L225B7BM680-DB

OR3L225B7BM680-DB

更新时间： 2024-01-27 08:16:59

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		时钟可编程逻辑
页数	文件大小	规格书
90页	2579K
描述
FPGA, 1444 CLBS, 166000 GATES, 266.4MHz, PBGA680, PLASTIC, BGAM-680

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OR3L225B7BM680-DB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	PLASTIC, BGAM-680
针数：	680	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.84	其他特性：	MAXIMUM USABLE GATES=340000
最大时钟频率：	266.4 MHz	CLB-Max的组合延迟：	1.03 ns
JESD-30 代码：	S-PBGA-B680	JESD-609代码：	e0
长度：	35 mm	湿度敏感等级：	3
可配置逻辑块数量：	1444	等效关口数量：	166000
输入次数：	442	逻辑单元数量：	11552
输出次数：	442	端子数量：	680
最高工作温度：	70 °C	最低工作温度：
组织：	1444 CLBS, 166000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA680,34X34,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5,3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.51 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	35 mm
Base Number Matches：	1

OR3L225B7BM680-DB 数据手册

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Data Addendum

March 2002

ORCA OR3LxxxB Series FPGAs

Features (continued)

■ Dual-use microprocessor interface (MPI) can be

used for conﬁguration, readback, device control, and

device status, as well as for a general-purpose inter-

face to the FPGA. Glueless interface to i960* and

PowerPC^†processors with user-conﬁgurable

address space provided.

■ Programmable I/O (PIO) has:

— Fast-capture input latch and input ﬂip-ﬂop (FF)/

latch for reduced input setup time and zero hold

time.

— Capability to (de)multiplex I/O signals.

— Fast access to SLIC for decodes and PAL-like

functions.

— Output FF and two-signal function generator to

reduce CLK to output propagation delay.

— Fast open-drain drive capability.

■ Parallel readback of conﬁguration data capability with

the built-in microprocessor interface.

■ Programmable clock manager (PCM) adjusts clock

phase and duty cycle for input clock rates from

5 MHz to 120 MHz. The PCM may be combined with

FPGA logic to create complex functions, such as dig-

ital phase-locked loops (DPLL), frequency counters,

and frequency synthesizers.Two PCMs are provided

per device.

■ New programmable I/O 3-state FF allows 3-state

buffer control signals to be set up a clock cycle early

for improved clock to output delays.

■ True internal 3-state, bidirectional buses with simple

System-Level Features

control provided by the SLIC.

■ 32 × 4 RAM per PFU, conﬁgurable as single- or dual-

port. Create large, fast RAM/ROM blocks (128 × 8 in

only eight PFUs) using the SLIC decoders as bank

drivers.

System-level features reduce glue logic requirements

and make a system on a chip possible. These features

in the ORCA OR3LxxxB include the following:

■ Full PCI local bus compliance for all devices in

3.3 V and 5 V PCI systems. Pin-selectable I/O

clamping diodes provide 3.3 V and 5 V compliance

and 5 V tolerance.

■ Full UTOPIA Level III I/O compliance (6.0 ns

CLK -> OUT, 2.0 ns setup with 0 ns hold).

* i960 is a registered trademark of Intel Corporation.

† PowerPC is a registered trademark of International Business

Machines, Inc.

Table 2. ORCA Series 3L System Performance

Parameter

# PFUs

-7

-8

Unit

16-bit Loadable Up/Down Counter

16-bit Accumulator

151

176

MHz

8 × 8 Parallel Multiplier:

Multiplier Mode, Unpipelined¹

ROM Mode, Unpipelined²

Multiplier Mode, Pipelined³

32 × 16 RAM (synchronous):

Single-port, 3-state Bus⁴

Dual-port⁵

11.5

129

116

152

MHz

173

231

209

277

MHz

128 × 8 RAM (synchronous):

Single-port, 3-state Bus⁴

Dual-port⁵

151

181

MHz

8-bit Address Decode (internal):

Using Softwired LUTs

Using SLICs⁶

0.25

2.30

1.29

2.00

1.12

32-bit Address Decode (internal):

Using Softwired LUTs

Using SLICs⁷

7.97

3.75

7.97

6.84

3.16

6.84

36-bit Parity Check (internal)

1. Implemented using 8 × 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.

2. Implemented using two 32 × 12 ROMs and one 12-bit adder, one 8-bit input, one ﬁxed operand, one 16-bit output.

3. Implemented using 8 × 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs contain

only pipelining registers).

4. Implemented using 32 × 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.

5. Implemented using 32 × 4 dual-port RAM mode.

6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.

7. Implemented in ﬁve partially occupied SLICs.

Lattice Semiconductor

1...3 4 567 8 9...90

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与OR3L225B7BM680-DB相关器件

型号	品牌	描述	获取价格	数据表
OR3L225B-7BM680I	LATTICE	Field Programmable Gate Array, 11552-Cell, CMOS, PBGA680	获取价格
OR3L225B7BM680I-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, 11552-Cell, CMOS, PBGA68	获取价格
OR3L225B7PS432-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA432, EBGA-432	获取价格
OR3L225B7PS432I-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA432, EBGA-432	获取价格
OR3L225B7PS680-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA680, PLASTIC, BGAM-6	获取价格
OR3L225B7PS680I-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA680, PLASTIC, BGAM-6	获取价格

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