Datasheet > OR3L225B7BM680-DB

OR3L225B7BM680-DB

更新时间： 2024-02-26 21:40:35

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		时钟可编程逻辑
页数	文件大小	规格书
90页	2579K
描述
FPGA, 1444 CLBS, 166000 GATES, 266.4MHz, PBGA680, PLASTIC, BGAM-680

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OR3L225B7BM680-DB 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	PLASTIC, BGAM-680
针数：	680	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.84	其他特性：	MAXIMUM USABLE GATES=340000
最大时钟频率：	266.4 MHz	CLB-Max的组合延迟：	1.03 ns
JESD-30 代码：	S-PBGA-B680	JESD-609代码：	e0
长度：	35 mm	湿度敏感等级：	3
可配置逻辑块数量：	1444	等效关口数量：	166000
输入次数：	442	逻辑单元数量：	11552
输出次数：	442	端子数量：	680
最高工作温度：	70 °C	最低工作温度：
组织：	1444 CLBS, 166000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA680,34X34,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5,3.3 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	2.51 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	35 mm
Base Number Matches：	1

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Data Addendum

March 2002

ORCA^®OR3LxxxB Series

Field-Programmable Gate Arrays

shared inputs and the logic ﬂexibility of LUTs with

independent inputs.

Introduction

■ Fast-carry logic and routing to adjacent PFUs for

nibble-wide, byte-wide, or longer arithmetic func-

tions, with the option to register the PFU carry-out.

■ Softwired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU.

■ Supplemental logic and interconnect cell (SLIC)

provides 3-statable buffers, up to 10-bit decoder,

and PAL*-like AND-OR-INVERT (AOI) in each pro-

grammable logic cell (PLC).

■ Abundant hierarchical routing resources based on

routing two data nibbles and two control lines per

set provide for faster place and route implementa-

tions and less routing delay.

■ Individually programmable drive capability: 12 mA

sink/6 mA source or 6 mA sink/3 mA source.

■ Built-in boundary scan (IEEE ^†1149.1 JTAG) and

testability function to 3-state all I/O pins.

■ Enhanced system clock routing for low-skew, high-

speed clocks originating on-chip or at any I/O.

■ Up to four ExpressCLK inputs allow extremely fast

clocking of signals on- and off-chip plus access to

internal general clock routing.

This data addendum refers to the information found

in the ORCA Series 3C and 3T Field-Programmable

Gate Arrays Data Sheet.

Features

■ High-performance, cost-effective, 0.25 µm 5-level

metal technology.

■ 2.5 V internal supply voltage and 3.3 V I/O supply

voltage for speed and compatibility.

■ Up to 340,000 usable gates^‡in 0.25 µm.

■ Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os

are 5 V tolerant to allow interconnection to both

3.3 V and 5 V devices, selectable on a per-pin

basis, when using 3.3 V I/O supply.)

■ Twin-quad programmable function unit (PFU)

architecture with eight 16-bit look-up tables (LUTs)

per PFU, organized in two nibbles for use in nibble-

or byte-wide functions. Allows for mixed arithmetic

and logic functions in a single PFU.

■ Nine user registers per PFU, one following each

LUT, plus one extra. All have programmable clock

enable and local set/reset, plus a global set/reset

that can be disabled per PFU.

■ StopCLK feature to glitchlessly stop/start the

ExpressCLKs independently by user command.

* PAL is a trademark of Lattice Semiconductor

†IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

■ Flexible input structure (FINS) of the PFUs pro-

vides a routability enhancement for LUTs with

Table 1. ORCA OR3LxxxB Series FPGAs

System

Max User

RAM

Process

Technology

Device

LUTs

Registers

User I/Os Array Size

Gates^‡

OR3L165B 120K—244K

OR3L225B 166K—340K 11552

8192

10752

14820

131K

185K

516

612

32 × 32

38 × 38

0.25 µm/5 LM

‡The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.

The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and

12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output

logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 × 4 RAM

(or 512 gates) per PFU.

1 234 5 6 7...90

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与OR3L225B7BM680-DB相关器件

型号	品牌	描述	获取价格	数据表
OR3L225B-7BM680I	LATTICE	Field Programmable Gate Array, 11552-Cell, CMOS, PBGA680	获取价格
OR3L225B7BM680I-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, 11552-Cell, CMOS, PBGA68	获取价格
OR3L225B7PS432-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA432, EBGA-432	获取价格
OR3L225B7PS432I-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA432, EBGA-432	获取价格
OR3L225B7PS680-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA680, PLASTIC, BGAM-6	获取价格
OR3L225B7PS680I-DB	LATTICE	Field Programmable Gate Array, 1444 CLBs, 166000 Gates, 266.4MHz, PBGA680, PLASTIC, BGAM-6	获取价格

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