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NVD5C434N

更新时间: 2024-11-10 01:18:19
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
6页 90K
描述
Power MOSFET

NVD5C434N 数据手册

 浏览型号NVD5C434N的Datasheet PDF文件第2页浏览型号NVD5C434N的Datasheet PDF文件第3页浏览型号NVD5C434N的Datasheet PDF文件第4页浏览型号NVD5C434N的Datasheet PDF文件第5页浏览型号NVD5C434N的Datasheet PDF文件第6页 
NVD5C434N  
Power MOSFET  
40 V, 2.1 mW, 163 A, Single N−Channel  
Features  
Low R  
to Minimize Conduction Losses  
Low Q and Capacitance to Minimize Driver Losses  
DS(on)  
G
www.onsemi.com  
AEC−Q101 Qualified and PPAP Capable  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
V
R
I
D
(BR)DSS  
DS(on)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
40 V  
2.1 mW @ 10 V  
163 A  
J
Parameter  
Drain−to−Source Voltage  
Symbol  
Value  
40  
Unit  
V
V
DSS  
D
Gate−to−Source Voltage  
Continuous Drain Cur-  
V
"20  
163  
115  
117  
58  
V
GS  
T
= 25°C  
= 100°C  
= 25°C  
I
A
C
D
rent R  
(Notes 1 & 3)  
q
JC  
T
C
Steady  
State  
G
Power Dissipation R  
(Note 1)  
T
C
P
W
A
q
D
JC  
T
C
= 100°C  
S
N−CHANNEL MOSFET  
Continuous Drain  
Current R  
T = 25°C  
A
I
26  
D
q
JA  
T = 100°C  
A
22  
(Notes 1, 2 & 3)  
Steady  
State  
4
Power Dissipation R  
(Notes 1 & 2)  
T = 25°C  
A
P
3.2  
W
q
D
JA  
T = 100°C  
A
2.2  
2
1
3
Pulsed Drain Current  
T = 25°C, t = 10 ms  
I
DM  
900  
A
A
p
DPAK  
CASE 369C  
STYLE 2  
Operating Junction and Storage Temperature  
T , T  
55 to  
175  
°C  
J
stg  
Source Current (Body Diode)  
I
S
130  
420  
A
Single Pulse Drain−to−Source Avalanche  
E
AS  
mJ  
MARKING DIAGRAM  
& PIN ASSIGNMENT  
Energy (T = 25°C, I  
= 25 A)  
J
L(pk)  
Lead Temperature for Soldering Purposes  
(1/8from case for 10 s)  
T
L
260  
°C  
4
Drain  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
THERMAL RESISTANCE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
1.28  
48  
Unit  
2
Drain  
Junction−to−Case (Drain) (Note 1)  
Junction−to−Ambient − Steady State (Note 2)  
R
°C/W  
1
3
q
JC  
JA  
Gate Source  
R
q
A
Y
WW  
= Assembly Location  
= Year  
= Work Week  
1. The entire application environment impacts the thermal resistance values shown,  
they are not constants and are only valid for the particular conditions noted.  
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.  
3. Maximum current for pulses as long as 1 second is higher but is dependent  
on pulse duration and duty cycle.  
2
5C434N= Device Code  
G
= Pb−Free Package  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
January, 2017 − Rev. 0  
NVD5C434N/D  
 

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