NV25256WF
256-Kb SPI Serial
Automotive EEPROM in
Wettable Flank Package
Description
The NV25256 is a 256−Kb Serial CMOS EEPROM device
internally organized as 32Kx8 bits. This features a 64−byte page write
buffer and supports the Serial Peripheral Interface (SPI) protocol. The
device is enabled through a Chip Select (CS) input. In addition, the
required bus signals are clock input (SCK), data input (SI) and data
output (SO) lines. The HOLD input may be used to pause any serial
communication with the NV25256 device. The device features
software and hardware write protection, including partial as well as
full array protection.
www.onsemi.com
1
UDFN8
(Wettable Flank)
MUW3 SUFFIX
CASE 517DH
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
PIN CONFIGURATIONS
Features
• Automotive Temperature Grade 1 (−40°C to +125°C)
• 10 MHz (5 V) SPI Compatible
V
CS
SO
1
CC
HOLD
SCK
SI
WP
• 1.8 V to 5.5 V Supply Voltage Range
• SPI Modes (0,0) & (1,1)
V
SS
UDFN8 (MUW3)
• 64−byte Page Write Buffer
(Top View)
• Additional Identification Page with Permanent Write Protection
• Self−timed Write Cycle
PIN FUNCTION
• Hardware and Software Protection
Pin Name
Function
Chip Select
• Block Write Protection
CS
SO
WP
− Protect 1/4, 1/2 or Entire EEPROM Array
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
Serial Data Output
Write Protect
• 100 Year Data Retention
V
SS
Ground
• 8−pad Wettable Flank UDFN 2x3 mm Package
SI
Serial Data Input
Serial Clock
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
SCK
Compliant
HOLD
Hold Transmission Input
Power Supply
V
CC
V
CC
SI
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
CS
SO
NV25256WF
WP
HOLD
SCK
V
SS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
January, 2018 − Rev. 1
NV25256/D