NTC Proprietary
Level: Property
DDR3(L) 2Gb SDRAM
NT5CB(C)256M8IN / NT5CB(C)128M16IP
Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM
Features
Signal Integrity
JEDEC DDR3 Compliant
- Configurable DS for system compatibility
- Configurable On-Die Termination
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings 6
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Read Leveling via MPR
Interface and Power Supply
- Partial Array Self Refresh (PASR) 1
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1353 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
- Power Down Mode
Options
Speed Grade (CL-TRCD-TRP) 2
Temperature Range (Tc) 4
- Commercial Grade = 0℃~95℃
- 2133 Mbps / 14-14-14
- 1866 Mbps / 13-13-13
- 1600 Mbps / 11-11-11
- Quasi Industrial Grade (-T) = -40℃~95℃
- Industrial Grade (-I) = -40℃~95℃
- Automotive Grade 2 (-H) = -40℃~105℃
- Automotive Grade 3 (-A) = -40℃~95℃
Programmable Functions
Self RefreshTemperature Range(Normal/Extended)
CAS Latency (6/7/8/9/10/11/13/14)
CAS Write Latency (5/6/7/8/9/10)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Packages / Density Information
Density and Addressing
256Mb x 8
Lead-free RoHS compliance and Halogen-free
Organization
128Mb x 16
2Gb
Length x Width
(mm)
Ball pitch
(mm)
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page Size
BA0 – BA2
A10 / AP
A12 /
A0 – A14
A0 – A9
1KB
BA0 – BA2
A10 / AP
A12 /
A0 – A13
A0 – A9
2KB
(Org. / Package)
78-ball
256Mbx8
8.00 x 10.50
8.00 x 13.00
0.80
0.80
VFBGA
96-ball
tREFI(us) 4
Tc<=85℃:7.8, Tc>85℃:3.9
160ns
128Mbx16
VFBGA
tRFC(ns) 5
NOTE 1 Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
NOTE 2 Please refer to ordering information for the detail.
NOTE 3 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. Please refer to page 5 operating frequency table.1.35V DDR3L-RS parts are exceptional
and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.
NOTE 4 If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
NOTE 5 Violating tRFC specification will induce malfunction.
NOTE 6 Only Support prime DQ’s feedback for each byte lane.
Version 2.1
07/2017
1
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NTC has the rights to change any specifications or product without notification.