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NT5CB128M16JQ-DIB PDF预览

NT5CB128M16JQ-DIB

更新时间: 2024-11-25 00:39:11
品牌 Logo 应用领域
南亚科技 - NANYA 动态存储器双倍数据速率
页数 文件大小 规格书
157页 4916K
描述
Commercial and Industrial DDR3(L) 2Gb SDRAM

NT5CB128M16JQ-DIB 数据手册

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NTC Proprietary  
Level: Property  
DDR3(L)-2Gb J-Die  
NT5CB(C)256M8JQ/NT5CB(C)128M16JR  
Commercial and Industrial DDR3(L) 2Gb SDRAM  
Features  
Signal Integrity  
Basis DDR3 Compliant  
- Configurable DS for system compatibility  
- Configurable On-Die Termination  
- 8n Prefetch Architecture  
- Differential Clock(CK/) and Data Strobe(DQS/)  
- Double-data rate on DQs, DQS and DM  
Data Integrity  
- ZQ Calibration for DS/ODT impedance accuracy via  
external ZQ pad (240 ohm ± 1%)  
Signal Synchronization  
- Write Leveling via MR settings 5  
- Auto Self Refresh (ASR) by DRAM built-in TS  
- Auto Refresh and Self Refresh Modes  
Power Saving Mode  
- Read Leveling via MPR  
Interface and Power Supply  
- Power Down Mode  
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)  
- SSTL_1353 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)  
Programmable Functions  
CAS Latency (6/7/8/9/10/11/13/14)  
CAS Write Latency (5/6/7/8/9/10)  
Self RefreshTemperature Range(Normal/Extended)  
Output Driver Impedance (34/40)  
Additive Latency (0/CL-1/CL-2)  
On-Die Termination of Rtt_Nom(20/30/40/60/120)  
On-Die Termination of Rtt_WR(60/120)  
Precharge Power Down (slow/fast)  
Write Recovery Time (5/6/7/8/10/12/14/16)  
Burst Type (Sequential/Interleaved)  
Burst Length (BL8/BC4/BC4 or 8 on the fly)  
Option  
Speed Grade (CL-TRCD-TRP) 1  
Temperature Range (Tc) 3,6  
- 2133 Mbps / 14-14-14  
- 1866 Mbps / 13-13-13  
- 1600 Mbps / 11-11-11  
- Commercial Grade : 0~95℃  
- Quasi Industrial Grade (-T) : -40~95℃  
- Industrial Grade (-I) : -40~95℃  
Package Informatiom  
Density and Addressing  
Lead-free RoHS compliance and Halogen-free  
Organization  
256Mb x 8  
128Mb x 16  
TFBGA  
Length x Width  
(mm)  
Ball pitch  
(mm)  
Bank Address  
Auto precharge  
BL switch on the fly  
Row Address  
Column Address  
Page Size  
BA0 BA2  
A10 / AP  
A12 /   
A0 A14  
A0 A9  
1KB  
BA0 BA2  
A10 / AP  
A12 /   
A0 A13  
A0 A9  
2KB  
Package  
7.50 x 10.50  
7.50 x 13.00  
0.80  
0.80  
78-Ball  
96-Ball  
tREFI(us) 3  
Tc<=85:7.8, Tc>85:3.9  
160ns  
tRFC(ns) 4  
NOTE 1 Please refer to ordering information for the detail.  
NOTE 2 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. Please refer to page 5 operating frequency table.1.35V DDR3L-RS parts are exceptional  
and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.  
NOTE 3 If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.  
NOTE 4 Violating tRFC specification will induce malfunction.  
NOTE 5 Only Support prime DQs feedback for each byte lane.  
NOTE 6 When operate above 95,AC/DC will be derated (increased) and reliability may be affected.  
Version 1.5  
04/2019  
1
Nanya Technology Cooperation ©  
NTC has the rights to change any specifications or product without notification.  
All Rights Reserved.  

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