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NSC800D-3I PDF预览

NSC800D-3I

更新时间: 2024-09-17 15:46:55
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
76页 780K
描述
IC 8-BIT, 2.5 MHz, MICROPROCESSOR, CDIP40, HERMETIC SEALED, CERAMIC, DIP-40, Microprocessor

NSC800D-3I 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP40,.6Reach Compliance Code:unknown
风险等级:5.89地址总线宽度:16
位大小:8边界扫描:NO
最大时钟频率:5 MHz外部数据总线宽度:8
格式:FIXED POINT集成缓存:NO
JESD-30 代码:R-CDIP-T40JESD-609代码:e0
低功率模式:YESDMA 通道数量:
外部中断装置数量:5串行 I/O 数:
端子数量:40片上数据RAM宽度:
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP40,.6封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not QualifiedRAM(字数):0
座面最大高度:5.08 mm速度:2.5 MHz
子类别:Microprocessors最大压摆率:15 mA
最大供电电压:6 V最小供电电压:2.4 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm
uPs/uCs/外围集成电路类型:MICROPROCESSORBase Number Matches:1

NSC800D-3I 数据手册

 浏览型号NSC800D-3I的Datasheet PDF文件第2页浏览型号NSC800D-3I的Datasheet PDF文件第3页浏览型号NSC800D-3I的Datasheet PDF文件第4页浏览型号NSC800D-3I的Datasheet PDF文件第5页浏览型号NSC800D-3I的Datasheet PDF文件第6页浏览型号NSC800D-3I的Datasheet PDF文件第7页 
June 1992  
NSC800TM High-Performance  
Low-Power CMOS Microprocessor  
General Description  
Features  
Y
Fully compatible with Z80 instruction set:  
É
The NSC800 is an 8-bit CMOS microprocessor that func-  
tions as the central processing unit (CPU) in National Semi-  
conductor’s NSC800 microcomputer family. National’s  
microCMOS technology used to fabricate this device pro-  
vides system designers with performance equivalent to  
comparable NMOS products, but with the low power advan-  
tage of CMOS. Some of the many system functions incorpo-  
rated on the device, are vectored priority interrupts, refresh  
control, power-save feature and interrupt acknowledge. The  
NSC800 is available in dual-in-line and surface mounted  
chip carrier packages.  
Powerful set of 158 instructions  
10 addressing modes  
22 internal registers  
Y
Y
Y
Y
Y
Y
Y
Y
Low power: 50 mW at 5V V  
Unique power-save feature  
Multiplexed bus structure  
CC  
Schmitt trigger input on reset  
On-chip bus controller and clock generator  
b
Variable power supply 2.4V 6.0V  
On-chip 8-bit dynamic RAM refresh circuitry  
The system designer can choose not only from the dedicat-  
ed CMOS peripherals that allow direct interfacing to the  
NSC800 but from the full line of National’s CMOS products  
to allow a low-power system solution. The dedicated periph-  
erals include NSC810A RAM I/O Timer, NSC858 UART,  
and NSC831 I/O.  
Speed: 1.0 ms instruction cycle at 4.0 MHz  
NSC800-4 4.0 MHz  
NSC800-35 3.5 MHz  
NSC800-3  
NSC800-1  
2.5 MHz  
1.0 MHz  
Y
Y
Capable of addressing 64k bytes of memory and 256  
I/O devices  
All devices are available in commercial, industrial and mili-  
tary temperature ranges along with two added reliability  
flows. The first is an extended burn in test and the second is  
the military class C screening in accordance with Method  
5004 of MIL-STD-883.  
Five interrupt request lines on-chip  
Block Diagram  
TL/C/517173  
NSC800TM is a trademark of National Semiconductor Corp.  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
Z80É is a registered trademark of Zilog Corp.  
C
1995 National Semiconductor Corporation  
TL/C/5171  
RRD-B30M105/Printed in U. S. A.  

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