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NLX1G11CMUTCG PDF预览

NLX1G11CMUTCG

更新时间: 2024-12-01 01:11:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 77K
描述
3-Input AND Gate

NLX1G11CMUTCG 技术参数

是否无铅: 不含铅生命周期:End Of Life
零件包装代码:DFN包装说明:VSON, SOLCC6,.04,14
针数:6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:6.25
系列:1GJESD-30 代码:S-PDSO-N6
长度:1 mm负载电容(CL):15 pF
逻辑集成电路类型:AND GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
输入次数:3端子数量:6
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装等效代码:SOLCC6,.04,14封装形状:SQUARE
封装形式:SMALL OUTLINE, VERY THIN PROFILE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8/5 V
Prop。Delay @ Nom-Sup:19 ns传播延迟(tpd):19 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:0.55 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Gold/Palladium (Ni/Au/Pd)端子形式:NO LEAD
端子节距:0.35 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1 mm
Base Number Matches:1

NLX1G11CMUTCG 数据手册

 浏览型号NLX1G11CMUTCG的Datasheet PDF文件第2页浏览型号NLX1G11CMUTCG的Datasheet PDF文件第3页浏览型号NLX1G11CMUTCG的Datasheet PDF文件第4页浏览型号NLX1G11CMUTCG的Datasheet PDF文件第5页浏览型号NLX1G11CMUTCG的Datasheet PDF文件第6页浏览型号NLX1G11CMUTCG的Datasheet PDF文件第7页 
NLX1G11  
3-Input AND Gate  
The NLX1G11 is an advanced high−speed 3−input CMOS AND  
gate in ultra−small footprint.  
The NLX1G11 input structures provide protection when voltages up  
to 7.0 V are applied, regardless of the supply voltage.  
Features  
www.onsemi.com  
High Speed: t = 2.4 ns (Typ) @ V = 5.0 V  
PD  
CC  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
MARKING  
DIAGRAMS  
24 mA Balanced Output Source and Sink Capability  
Balanced Propagation Delays  
UDFN6  
1.0 x 1.0  
CASE 517BX  
M
Overvoltage Tolerant (OVT) Input Pins  
Ultra−Small Packages  
1
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q101  
Qualified and PPAP Capable  
UDFN6  
1.2 x 1.0  
CASE 517AA  
X M  
These are Pb−Free Devices  
1
UDFN6  
1.45 x 1.0  
CASE 517AQ  
P
M
A
GND  
B
1
2
3
6
5
C
1
X
M
G
= Device Marking  
= Date Code  
= Pb−Free Package  
V
CC  
A
B
C
&
Y
4
Y
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
Figure 1. Pinout (Top View)  
PIN ASSIGNMENT  
Pin  
1
Function  
A
GND  
B
2
3
4
Y
5
V
CC  
6
C
FUNCTION TABLE  
Input  
Output  
Y
A
B
C
L
X
X
H
X
L
X
H
X
X
L
L
L
L
H
H
H − HIGH Logic Level  
L − LOW Logic Level  
X = Either LOW or HIGH Logic Level  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
June, 2016 − Rev. 5  
NLX1G11/D  

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