NLX1G74
Single D Flip-Flop
The NLX1G74 is a high performance, full function edge−triggered
D Flip−Flop in ultra−small footprint. The NLX1G74 input structures
provide protection when voltages up to 7.0 V are applied, regardless of
the supply voltage.
http://onsemi.com
Features
• Extremely High Speed: t = 2.6 ns (typical) at V = 5.0 V
PD
CC
MARKING
DIAGRAM
• Designed for 1.65 V to 5.5 V V Operation
CC
8
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
1
CC
A
1
UQFN8
MU SUFFIX
CASE 523AN
• 24 mA Balanced Output Sink and Source Capability at V = 3.0 V
AA MG
CC
G
• Balanced Propagation Delays
• Overvoltage Tolerant (OVT) Input Pins
• Ultra Small Package
AA= Device Code
M = Date Code*
G
• This is a Pb−Free Device
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT DIAGRAM
TRUTH TABLE
CP
7
D
6
Q
5
Inputs
Outputs
PR CLR CP
D
Q
Q
Operating Mode
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
Asynchronous Set
Asynchronous Clear
Undetermined
V
CC
8
4 GND
H
H
H
H
↑
↑
h
l
H
L
L
1
2
3
Q
H
Load and Read Register
Hold
PR CLR
H
H
↑
X
NC
NC
H
h
= High Voltage Level
= High Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
= Low Voltage Level
= Low Voltage Level One Setup Time Prior to the Low−to−High
Clock Transition
LOGIC DIAGRAM
PR
L
l
1
NC
X
↑
= No Change
D
6
Q
Q
3
5
= High or Low Voltage Level and Transitions are Acceptable
= Low−to−High Transition
= Not a Low−to−High Transition
7
CP
↑
For I reasons, DO NOT FLOAT Inputs
2
CC
V
CC
= 8, GND = 4
CLR
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
April, 2009 − Rev. 0
NLX1G74/D