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NLX2G00AMX1TCG PDF预览

NLX2G00AMX1TCG

更新时间: 2024-12-01 05:54:15
品牌 Logo 应用领域
安森美 - ONSEMI 栅极逻辑集成电路光电二极管
页数 文件大小 规格书
7页 132K
描述
Dual 2-Input NAND Gate

NLX2G00AMX1TCG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:1.45 X 1 MM, 0.35 MM PITCH, LEAD FREE, ULLGA-8针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.8
Is Samacsys:N系列:2G
JESD-30 代码:R-PDSO-N8JESD-609代码:e4
长度:1.45 mm逻辑集成电路类型:NAND GATE
湿度敏感等级:1功能数量:2
输入次数:2端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):10.5 ns
认证状态:Not Qualified座面最大高度:0.4 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.35 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1 mm
Base Number Matches:1

NLX2G00AMX1TCG 数据手册

 浏览型号NLX2G00AMX1TCG的Datasheet PDF文件第2页浏览型号NLX2G00AMX1TCG的Datasheet PDF文件第3页浏览型号NLX2G00AMX1TCG的Datasheet PDF文件第4页浏览型号NLX2G00AMX1TCG的Datasheet PDF文件第5页浏览型号NLX2G00AMX1TCG的Datasheet PDF文件第6页浏览型号NLX2G00AMX1TCG的Datasheet PDF文件第7页 
NLX2G00  
Dual 2-Input NAND Gate  
The NLX2G00 is an advanced high-speed dual 2-input CMOS  
NAND gate in ultra-small footprint.  
The NLX2G00 input structures provide protection when voltages up  
to 7.0 volts are applied, regardless of the supply voltage.  
http://onsemi.com  
MARKING  
Features  
High Speed: t 2.4 ns (typical) at V = 5.0 V  
PD  
CC  
DIAGRAMS  
Designed for 1.65 V to 5.5 V V Operation  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
ULLGA8  
1.45 x 1.0  
CASE 613AA  
QM  
G
24 mA Balanced Output Sink and Source Capability  
Balanced Propagation Delays  
1
Overvoltage Tolerant (OVT) Input Pins  
This is a PbFree Device  
ULLGA8  
1.6 x 1.0  
CASE 613AB  
AJM  
G
1
ULLGA8  
1.95 x 1.0  
CASE 613AC  
AHM  
G
1
A1  
B1  
1
2
3
4
8
7
6
5
V
CC  
XX  
M
G
= Specific Device Code  
= Date Code  
= PbFree Package  
Y1  
B2  
A2  
PIN ASSIGNMENT  
Pin  
Function  
1
A1  
Y2  
2
3
4
5
6
7
8
B1  
Y2  
GND  
A2  
GND  
B2  
Figure 1. Pinout  
Y1  
V
CC  
IEEE/IEC  
&
A1  
B1  
FUNCTION TABLE  
Y = AB  
Y1  
Y2  
A2  
B2  
Inputs  
Output  
A
B
L
Y
H
H
H
L
Figure 2. Logic Symbol  
L
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
© Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
December, 2009 Rev. 0  
NLX2G00/D  

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