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NLU1G86AMUTCG PDF预览

NLU1G86AMUTCG

更新时间: 2024-11-04 01:11:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路石英晶振触发器
页数 文件大小 规格书
7页 145K
描述
Single 2-Input Exclusive OR Gate

NLU1G86AMUTCG 技术参数

是否无铅: 不含铅生命周期:End Of Life
零件包装代码:DFN包装说明:VSON, SOLCC6,.04,20
针数:6Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.61
系列:1GJESD-30 代码:R-PDSO-N6
JESD-609代码:e4长度:1.45 mm
负载电容(CL):50 pF逻辑集成电路类型:XOR GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1输入次数:2
端子数量:6最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC6,.04,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL电源:1.8/5 V
Prop。Delay @ Nom-Sup:19.5 ns传播延迟(tpd):19.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:0.55 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
宽度:1 mmBase Number Matches:1

NLU1G86AMUTCG 数据手册

 浏览型号NLU1G86AMUTCG的Datasheet PDF文件第2页浏览型号NLU1G86AMUTCG的Datasheet PDF文件第3页浏览型号NLU1G86AMUTCG的Datasheet PDF文件第4页浏览型号NLU1G86AMUTCG的Datasheet PDF文件第5页浏览型号NLU1G86AMUTCG的Datasheet PDF文件第6页浏览型号NLU1G86AMUTCG的Datasheet PDF文件第7页 
NLU1G86  
Single 2-Input Exclusive OR  
Gate  
The NLU1G86 MiniGatet is an advanced highspeed CMOS  
2input Exclusive OR gate in ultrasmall footprint.  
The NLU1G86 input and output structures provide protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage.  
www.onsemi.com  
MARKING  
DIAGRAMS  
Features  
High Speed: t = 3.5 ns (Typ) @ V = 5.0 V  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
UDFN6  
1.0 x 1.0  
CASE 517BX  
Power Down Protection Provided on inputs  
X M  
X M  
X M  
Balanced Propagation Delays  
1
Overvoltage Tolerant (OVT) Input and Output Pins  
UltraSmall Packages  
UDFN6  
1.2 x 1.0  
CASE 517AA  
These are PbFree Devices  
1
UDFN6  
1.45 x 1.0  
CASE 517AQ  
IN B  
IN A  
GND  
1
2
3
6
5
V
CC  
1
NC  
4
M
= Device Marking  
= Date Code  
4
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 1. Pinout (Top View)  
IN A  
IN B  
= 1  
OUT Y  
Figure 2. Logic Symbol  
PIN ASSIGNMENT  
1
2
3
4
5
6
IN B  
IN A  
GND  
OUT Y  
NC  
V
CC  
FUNCTION TABLE  
Input  
Output  
A
B
Y
L
L
H
H
L
H
L
L
H
H
L
H
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
August, 2016 Rev. 3  
NLU1G86/D  

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