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NLU1G00AMUTCG PDF预览

NLU1G00AMUTCG

更新时间: 2024-11-03 01:22:39
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 142K
描述
Single 2-Input NAND Gate

NLU1G00AMUTCG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DFN
包装说明:VSON, SOLCC6,.04,20针数:6
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.71
系列:1GJESD-30 代码:R-PDSO-N6
JESD-609代码:e4长度:1.45 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1输入次数:2
端子数量:6最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC6,.04,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TAPE AND REEL电源:1.8/5 V
Prop。Delay @ Nom-Sup:16.5 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:0.4 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
宽度:1 mmBase Number Matches:1

NLU1G00AMUTCG 数据手册

 浏览型号NLU1G00AMUTCG的Datasheet PDF文件第2页浏览型号NLU1G00AMUTCG的Datasheet PDF文件第3页浏览型号NLU1G00AMUTCG的Datasheet PDF文件第4页浏览型号NLU1G00AMUTCG的Datasheet PDF文件第5页浏览型号NLU1G00AMUTCG的Datasheet PDF文件第6页浏览型号NLU1G00AMUTCG的Datasheet PDF文件第7页 
NLU1G00  
Single 2-Input NAND Gate  
The NLU1G00 MiniGatet is an advanced highspeed CMOS  
2input NAND gate in ultrasmall footprint.  
The NLU1G00 input and output structures provide protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage.  
www.onsemi.com  
Features  
High Speed: t = 3.5 ns (Typ) @ V = 5.0 V  
PD  
CC  
MARKING  
DIAGRAMS  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
Power Down Protection Provided on inputs  
Balanced Propagation Delays  
UDFN6  
1.2 x 1.0  
CASE 517AA  
Q
M
Overvoltage Tolerant (OVT) Input and Output Pins  
UltraSmall Packages  
1
UDFN6  
1.0 x 1.0  
CASE 517BX  
M
These are PbFree Devices  
1
IN B  
IN A  
GND  
1
2
3
6
5
V
CC  
UDFN6  
1.45 x 1.0  
CASE 517AQ  
Q
M
1
NC  
T
M
= Device Marking  
= Date Code  
4
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 4 of  
this data sheet.  
Figure 1. Pinout (Top View)  
IN A  
IN B  
&
OUT Y  
Figure 2. Logic Symbol  
PIN ASSIGNMENT  
1
2
3
4
5
6
IN B  
IN A  
GND  
OUT Y  
NC  
V
CC  
FUNCTION TABLE  
Input  
Output  
A
B
Y
L
L
H
H
L
H
L
H
H
H
L
H
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
June, 2016 Rev. 3  
NLU1G00/D  

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