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NL74VCX16373DT PDF预览

NL74VCX16373DT

更新时间: 2024-01-14 19:33:16
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
12页 276K
描述
ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48

NL74VCX16373DT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.2
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
负载电容(CL):30 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:2端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:RAIL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:3 ns
传播延迟(tpd):7.8 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.1 mm
Base Number Matches:1

NL74VCX16373DT 数据手册

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With 3.6V–Tolerant Inputs and Outputs  
(3–State, Non–Inverting)  
The NL74VCX16373 is an advanced performance, non–inverting  
16–bit transparent latch. It is designed for very high–speed, very  
low–power operation in 1.8V, 2.5V or 3.3V systems. The VCX16373  
is byte controlled, with each byte functioning identically, but  
independently. Each byte has separate Output Enable and Latch  
Enable inputs. These control pins can be tied together for full 16–bit  
operation.  
When operating at 2.5V (or 1.8V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.  
The NL74VCX16373 contains 16 D–type latches with 3–state  
3.6V–tolerant outputs. When the Latch Enable (LEn) inputs are  
HIGH, data on the Dn inputs enters the latches. In this condition, the  
latches are transparent, (a latch output will change state each time its D  
input changes). When LE is LOW, the latch stores the information that  
was present on the D inputs a setup time preceding the  
HIGH–to–LOW transition of LE. The 3–state outputs are controlled  
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches.  
http://onsemi.com  
48  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
MARKING DIAGRAM  
48  
NL74VCX16373DT  
AWLYYWW  
1
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
Designed for Low Voltage Operation: V  
3.6V Tolerant Inputs and Outputs  
= 1.65–3.6V  
CC  
WW = Work Week  
High Speed Operation: 3.0ns max for 3.0 to 3.6V  
3.9ns max for 2.3 to 2.7V  
6.8ns max for 1.65 to 1.95V  
Static Drive: ±24mA Drive at 3.0V  
±18mA Drive at 2.3V  
PIN NAMES  
Pins  
Function  
OEn  
LEn  
D0–D15  
O0–O15  
Output Enable Inputs  
Latch Enable Inputs  
Inputs  
±6mA Drive at 1.65V  
Supports Live Insertion and Withdrawal  
Outputs  
I  
Specification Guarantees High Impedance When V = 0V  
OFF  
CC  
Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds ±300mA @ 125°C  
ORDERING INFORMATION  
Device  
Package  
TSSOP  
TSSOP  
Shipping  
39 / Rail  
ESD Performance: Human Body Model >2000V; Machine Model  
NL74VCX16373DT  
NL74VCX16373DTR  
>200V  
2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
July, 2000 – Rev. 1  
NL74VCX16373/D  

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