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NE568AN

更新时间： 2024-11-22 22:50:51
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管
页数 文件大小 规格书
9页 326K
描述
150MHz phase-locked loop

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中文翻译

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NE568AN 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：PLASTIC, SOT-146-1, DIP-20针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.82模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：R-PDIP-T20长度：26.73 mm
功能数量：1端子数量：20
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified座面最大高度：4.2 mm
子类别：PLL or Frequency Synthesis Circuits最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

NE568AN 数据手册

 浏览型号NE568AN的Datasheet PDF文件第2页浏览型号NE568AN的Datasheet PDF文件第3页浏览型号NE568AN的Datasheet PDF文件第4页浏览型号NE568AN的Datasheet PDF文件第5页浏览型号NE568AN的Datasheet PDF文件第6页浏览型号NE568AN的Datasheet PDF文件第7页 
Philips Semiconductors  
Product specification  
150MHz phase-locked loop  
NE/SA568A  
DESCRIPTION  
PIN CONFIGURATION  
The NE568A is a monolithic phase-locked loop (PLL) which  
operates from 1Hz to frequencies in excess of 150MHz and features  
an extended supply voltage range and a lower temperature  
D, N Packages  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
LF1  
LF2  
CC2  
coefficient of the V center frequency in comparison with its  
CO  
GND  
GND  
2
1
predecessor, the NE 568. The NE568A is function and  
3
LF3  
LF4  
pin-compatible with the NE568, requiring only minor changes in  
peripheral circuitry (see Figure 3). Temperature compensation  
network is different, no resistor on Pin 12, needs to be grounded and  
4
TCAP1  
5
TCAP2  
GND1  
FREQ ADJ  
Pin 13 has a 3.9kΩ resistor to ground. Timing cap, C , is different  
2
6
OUT  
FILT  
and for 70MHz operation with temperature compensation network  
should be 16pF, not 34pF as was used in the NE568. The NE568A  
7
V
V
OUT  
CC1  
has the following improvements: ESD protected; extended V  
CC  
8
REFBYP  
TC  
ADJ2  
range from 4.5V to 5.5V; operating temperature range -55 to 125°C  
(see Signetics Military 568A data sheet); less layout sensitivity; and  
9
PNPBYP  
INPBYP  
TC  
ADJ1  
10  
V
lower T of VCO (center frequency). The integrated circuit consists  
IN  
C
of a limiting amplifier, a current-controlled oscillator (ICO), a phase  
detector, a level shift circuit, V/I and I/V converters, an output buffer,  
and bias circuitry with temperature and frequency compensating  
characteristics. The design of the NE568A is particularly well-suited  
for demodulation of FM signals with extremely large deviation in  
systems which require a highly linear output. In satellite receiver  
applications with a 70MHz IF, the NE568A will demodulate ±20%  
deviations with less than 1.0% typical non-linearity. In addition to  
high linearity, the circuit has a loop filter which can be configured  
with series or shunt elements to optimize loop dynamic  
TOP VIEW  
SR01037  
Figure 1. Pin Configuration  
• Series or shunt loop filter component capability  
• External loop gain control  
• Temperature compensated  
1
• ESD protected  
performance. The NE568A is available in 20-pin dual in-line and  
20-pin SO (surface mounted) plastic packages.  
APPLICATIONS  
• Satellite receivers  
FEATURES  
• Operation to 150MHz  
• Fiber optic video links  
• VHF FSK demodulators  
• Clock Recovery  
• High linearity buffered output  
ORDERING INFORMATION  
DESCRIPTION  
20-Pin Plastic Small Outline Large (SOL) Package  
20-Pin Plastic Dual In-Line Package (DIP)  
20-Pin Plastic Small Outline Large (SOL) Package  
20-Pin Plastic Dual In-Line Package (DIP)  
TEMPERATURE RANGE  
0 to +70°C  
ORDER CODE  
NE568AD  
NE568AN  
SA568AD  
DWG #  
SOT163-1  
SOT146-1  
SOT163-1  
SOT146-1  
0 to +70°C  
-40 to +85°C  
-40 to +85°C  
SA568AN  
BLOCK DIAGRAM  
LF1  
20  
LF2  
19  
LF3  
18  
LF4  
17  
FREQ ADJ  
OUT  
V
TC  
TC  
V
FILT  
OUT  
14  
ADJ2  
13  
ADJ1  
12  
IN  
11  
16  
15  
LEVEL SHIFT  
TCADJ  
BIAS  
OUT  
BUF  
LEVEL SHIFT  
V/I  
I/V  
CONVERTER  
CONVERTER  
PHASE  
DETECTOR  
AMP  
NOTE:  
Pins 4 and 5 can tolerate  
1000V only, and all other  
pins, greater than 2000V  
for ESD (human body  
model).  
ICO  
1
2
GND  
3
4
TCAP1  
5
6
7
8
9
10  
INPBYP  
V
GND  
V
CC1  
GND1  
REFBYP  
PNPBYP  
TCAP2  
SR01038  
CC2  
2
1
Figure 2. Block Diagram  
1
1996 Feb 1  
853-1558 16328  
1234567...9

中文翻译

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